JPS5917875A - Programmable frequency generator for driving inverter with inductive load - Google Patents

Abstract

PURPOSE:To enable to variably alter a frequency division ratio without increasing components by sharing the operation of relatively low frequency for the frequency division by a microcomputer. CONSTITUTION:A frequency generated by a reference frequency oscillator 1 is inputted to the terminal CLK of a programmable counter 2, an address code is inputted from the outputs 00-07 of microcomputer 3 to the address inputs P0- P7 to determine the frequency division ratio. The direct output of the counter 2 and the output of a binary counter 4 are inputted to a selective output circuit 5. The output of the counter 4 is applied as an interrupt to the microcomputer 3. The output which is divided in frequency by the software of the microcomputer 3 is inputted to the circuit 5. The final frequency output is obtained from the circuit 5.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a programmable frequency generator for driving an inverter with an inductive load, such as a variable speed ETECON compressor motor.

Conventional configurations and their problems Conventionally, in order to configure a programmable timer with a wide frequency division ratio, the frequency division ratio must be set over a wide range as shown in Figure 1, or the frequency division ratio must be set over a wide range as shown in Figure 2. A low-bit programmable counter and a cascade connection θ of a binary counter and the like are known. By the way, the frequency output of the programmable counter p (1, t) divided by 5 is expressed by the following formula, where fosc is the reference frequency JhQ function fOUT is the frequency output, n is the frequency division ratio, a) Mano IJ 7 tresbinot number of the grammar pull counter is 1°. FIG. 1 is an example in which the number of address bits a in the above formula is increased.

In the circuit of FIG. 1, the reference oscillation section 1 has a frequency f. SC is generated and inputted to the programmable counter 2. On the other hand, the address P of the programmable counter 2 is input from the output terminal 0o-O(a-1) of the microcomputer 3. −”(
A binary address code is set in a-1).

fOUT is an output terminal obtained by dividing fO8c.

Here, if the address bit number a is 8, the frequency division ratio n is 1
~256, and if the number of address bits a is still 10, the division ratio n is 441 to 1023, and if the number of address bits a is 12, the division ratio n is 1 to 4095.
Is it possible to achieve the desired goal by appropriately selecting the number of address bits a? This structure is difficult to solve because there are no multi-bit programmable counters on the market, and the address of the microconbeater is This method has drawbacks such as an increase in the number of outputs and complicated software.

Next, the structure shown in FIG. 2 will be explained.

In the same figure, 1, 2, and 3Q, 1, the same reference oscillation unit, a programmable color/receiver, and a microcomputer as the first are shown, and 4 is a several-stage H/F nary counter unit. The output fOU・1・ of this circuit is the output of each stage of the binary counter section 4, which is connected to the output terminal O81 of the microcomputer 3.
- Selected output is performed by the output selection unit 5 which selects using OOx.

As an example, if the programmable counter 2 is 8 bits and fO3C/600 is required as the output fOUT, the frequency division range of the programmable counter 2 is such that the frequency division ratio n is 1.
~255, so the output is fOUT−fO8c/(
15o×2).

Therefore, the output terminals 07 to ○ of the microcomputer 3
. The address code i10010110 is output from the microcomputer 3, and the address code is
) can be obtained by setting "Hr+". Although this method has the advantage that the frequency division ratio can be created arbitrarily to some extent and can be configured using general-purpose ICs on the market, it requires a large number of parts and is difficult to use for microconverters. It also occupies a lot of output terminals, making it impractical.

OBJECT OF THE INVENTION The present invention aims to overcome the above-mentioned conventional drawbacks by using a general-purpose I(
The object of the present invention is to provide a programmable counter with a simple circuit configuration that does not place a large burden on the software of a microcomputer, does not occupy many output terminals, and has a simple circuit configuration.

Structure of the Invention The present invention synthesizes frequencies in a range that can be tracked sufficiently by a microcomputer by frequency division using microcomputer software, and then synthesizes frequencies in a range that can be tracked sufficiently by a microcomputer, and directly outputs all the outputs of a programmable counter. A cascade circuit of a programmable counter and a binary counter is configured with equal constraints, and an in/out circuit with an inductive load is
It synthesizes the frequencies that are added all at once, and allows software frequency division to be any integer (which allows for a higher degree of freedom than using an integer counter).

DESCRIPTION OF THE EMBODIMENTS As an embodiment of the present invention, the configuration of a PWM type original oscillation IEfil path of an inverter for a room air conditioner will be described below with reference to FIG. Here, the PWM method is an abbreviation for pulse width modulation method, and is a method in which a chopping algorithm of the voltage is configured so that the integral of the voltage over time, which instantly produces power, becomes almost a sine wave.

In the figure, 1 is a reference frequency generator that generates the reference frequency fO3c, 2 is a general-purpose programmable counter with a built-in inary counter, 3 is a P-MOS microcomputer, and 4 is a counter that is built in the programmable counter 2. Numeral counter 6 is a selection output circuit that switches and outputs booters f, f2, and f2 depending on the output frequency range.

In the above configuration, the frequency foSC generated from the reference frequency oscillator 1 is the CLK of the programmable counter 2.
The rear address code is input from the outputs O6 to ○7 of the micro combico and the outputs O6 to ○7 of the micro combico to the address manual power P0 to P, and the frequency divided by 71 is determined to be 1 and 2.

The direct output of the programmable counter 2 is fl, and the output of the binary counter 4 built into the programmable counter 2 is f2. has been entered. The output f2 is frequency-divided by the software of the microcomputer 3 and the final frequency output fOUT is output from the output terminal O81 of the microcomputer 3 depending on the frequency range.
It is selectively outputted via the selective output circuit 5 specified by ~oo3.

Here, 1 l-fosc/n (n-1 to 255).

f 2 ”” f OS C/ (2X n ) (n
-1~255), f3-fO8c/(2XnXm)(
n=1-255. m=1.

2.3...). Incidentally, n is an inary coat added to the address input (Po-P7) of the programmable counter 2, and m (tl is the frequency division ratio by software of the microcomputer 3).

Here, the microcomputer 3 usually has control over other systems and cannot operate at such high speeds, so the output f2 must be set at a relatively low frequency when the output f3 is output.

The PWM method of inverters for room air conditioners usually uses the motor's synchronous frequency f. In many cases, the original oscillation is obtained by multiplying
In the figure, the carrier is 42, f
03 c = 320 KHZ, convert frequency output @ to synchronous frequency! ') IH as 1 no C12~90H2
It is designed so that the output -C can be turned off at the z step. 71 in the frequency division ratio column; 85 to 254 in the first term is the programmable counter frequency division ratio, 2 in the second term is the output specification of the binary counter attached to the programmable counter,
g("r 3 JA's multiplier of 2 indicates the frequency division ratio by the sonotoware of the microconbeater.

Here, the common use as an air conditioner is 1t41j & 15H if it is converted to the synchronous frequency of the motor and is 30 to 90Hz.
Since the frequency less than z is used only at the time of starting, while the motor is under normal rotational control, the microcombeater only needs to specify the address and the output of fl while the motor is under normal rotational control.

Furthermore, from Fig. 4, at the time of output 13, the maximum value of the frequency input to the microconbeater is f()Bc/(
2X 136) #1.1 KHz, which is a value that can be sufficiently followed and processed even by a commercially available 4-bit microconbeater. It's a moat, and the Micro Combita 3 is here.

If f3 is not an interrupt input, a software timer can also be used to synthesize the output f3. In this case as well, the burden on the software is small because it is only at the time of startup.

Effects of the Invention According to the present invention, when an arbitrary frequency is generated by a programmable frequency generator, a relatively low frequency part is divided by a microconbeater.
The frequency division ratio of the system can be freely changed without increasing the number of components, and the software only requires frequency division processing when starting the motor, so there is less burden on the system.As a result, the basic programmable counter can be constructed from general-purpose, inexpensive components, resulting in a great cost advantage.
As a result, there is a higher degree of freedom in the division ratio compared to the conventional configuration of a programmable counter and a binary counter.Furthermore, when using interrupt input, the burden on software can be reduced by simply specifying the frequency division and selecting the output. Since it is small in size, it has various advantages such as being much simpler than using a multi-bit programmable counter.

[Brief explanation of the drawing]

1M and 2 are circuit diagrams of a programmable timer showing different conventional examples, FIG. 3 is a circuit diagram of a programmable frequency generator showing an embodiment of the present invention, and FIG. 4 is a specific example of the programmable frequency generator. It is an explanatory view showing an example of a lesson. 1... Reference frequency generator, 2... Programmable counter, 3... Microcomputer, 4... Binary counter, 5... Selective output circuit. Name of agent: Patent attorney Toshio Nakao and one other WS
Figure IFigure 3Figure 4

Claims (1)

[Claims] a programmable counter having an address input; and a microconbeater having a selection output; the address input of the programmable counter being operated by the microconbeater; By inputting the signal into the input terminal of the microconbeater, setting a fixed frequency as the branching frequency, setting the frequency above the branching frequency as the normal use range, setting the frequency below the branching frequency as the starting range, and switching the selected output of the microconbeater. , the normal use area has an inductive load that outputs the output of the program counter at t, and the start area has an inductive load including a frequency-divided output of the programmable counter by software of the microconbeater. Programmable frequency generator for inverter and drive.