JP3289921B2 - Programmable controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller for controlling the speed and position of a pulse motor, a DC motor or the like.

[0002]

2. Description of the Related Art In order to perform position control in a conventional programmable controller, it has been configured by hardware.

[0003]

However, the conventional method has a problem that a dedicated and expensive pulse output unit is required. The present invention has been made in view of the above points, and eliminates the need for an expensive pulse output-dedicated unit, makes it possible to control the speed and position of a pulse motor with only a CPU unit, and provides an inexpensive programmable controller. The purpose is to provide.

[0004]

According to the present invention, there is provided a pulse counter comprising a count register for counting an external pulse train, a target value register for generating a coincidence interrupt signal when a value coincides with the count register, and an internal clock. A pulse output section comprising: a count register for counting the count; a comparison register for outputting a match signal when the value matches the count register; and an output control circuit for inverting the output by the match signal to output a pulse and inputting the pulse to a pulse motor driver. The frequency data set in the operation memory area in advance by the user program and set in the comparison register of the pulse output unit and the target value data set in the target value register of the pulse counter are set as one set, and are continuously set for n sets. The pulse output unit is controlled while referring to the set table, When the number of pulses input from the pulse output unit to the count register of the pulse counter matches the value of the target value register, interrupt processing is performed with a coincidence interrupt signal from the pulse counter that is generated. CPU that switches to and sets the target value data
It is composed of

According to a second aspect of the present invention, a pulse counter consisting of a count register for counting a pulse train from the outside, a target value register for generating a coincidence interrupt signal when a value coincides with the count register, and an internal clock are counted. A count register, a comparison register that outputs a match signal when the value matches the count register, an output control circuit that inverts the output by the match signal, outputs a pulse with a duty ratio controlled to 50%, and inputs the pulse to a pulse motor driver And a frequency data set in a calculation memory area in advance by a user program and set in a comparison register of the pulse output unit and a target value data set in a target value register of the pulse counter.
The pulse output unit is controlled while referring to a table that is set continuously for n sets, and the number of pulses input from the pulse output unit to the count register of the pulse counter matches the value of the target value register. The interrupt processing is performed by a coincidence interrupt signal from the pulse counter which is generated at the time of the interruption, and the CPU switches to the next frequency data and target value data in the table and sets them.

According to a third aspect of the present invention, there is provided a pulse register comprising a count register for counting a pulse train from the outside, a target value register for generating a coincidence interrupt signal when a value coincides with the count register, and a count register for counting an internal clock. A comparison register for outputting a coincidence signal when the value coincides with the count register; an output control circuit for inverting the output by the coincidence signal to output a pulse whose duty ratio is controlled to other than 50% and inputting the pulse to the DC motor driver; And a set of the frequency data set in the operation memory area in advance by the user program and set in the comparison register of the pulse output unit and the target value data set in the target value register of the pulse counter. While referring to the table set continuously for the set, The pulse output unit is controlled, and the interrupt processing is performed by a match interrupt signal from the pulse counter generated when the number of pulses input to the count register of the pulse counter from the pulse output unit matches the value of the target value register. It is configured by a CPU that switches and sets the next frequency data and target value data in the table.

Further, a pulse counter comprising a count register for counting a pulse train from the outside, a target value register for generating a coincidence interrupt signal when a value coincides with the count register, and counting an internal clock. A count register, two comparison registers for outputting a coincidence signal when the value matches the count register, and an output control circuit for inverting the output according to the coincidence signal from the two comparison registers, outputting a pulse, and inputting the pulse to the pulse motor driver. Pulse output unit, frequency data set in the operation memory area in advance by the user program and set in the comparison register of the pulse output unit and target value data set in the target value register of the pulse counter are set to 1
The pulse output unit is controlled while referring to a table that is set continuously for n sets, and the number of pulses input from the pulse output unit to the count register of the pulse counter matches the value of the target value register. A programmable controller comprising: a CPU that performs interrupt processing with a coincidence interrupt signal from a pulse counter that is generated when switching to the next frequency data and target value data in a table and sets the CPU.

According to a fifth aspect of the present invention, a plurality of types of internal clocks input to the count register are provided, and a multiplexer for selecting an arbitrary internal clock is provided.

[0009]

[Operation] Thus, the frequency output and the target value data set in the operation memory area in advance by the user program are set as one set, and the pulse output unit is continuously referred to for n sets by referring to the set table. And the pulse output from the pulse output unit is input to the pulse counter, and when the pulse reaches the target value, the interrupt processing is started by the coincidence interrupt signal from the pulse counter, and the next data is referenced in that. Then, by switching the frequency of the output pulse, the frequency of the output pulse motor to the pulse motor driver is controlled, and the drive of the pulse motor is controlled.

According to a second aspect of the present invention, the pulse output unit sets the frequency data and the target value data set in the operation memory area in advance by the user program as one set, and refers to the set table continuously for n sets. Control the
When the duty ratio is controlled to 50% from the pulse output unit, the pulse is input to the pulse counter, and when the pulse reaches the target value, the interrupt processing is started by the coincidence interrupt signal from the pulse counter. Refer to the following data,
By switching the frequency of the output pulse, the frequency of the output pulse motor to the pulse motor driver is controlled, and the drive of the pulse motor is controlled.

In the present invention, the frequency data and the target value data previously set in the operation memory area by the user program are set as one set, and the set is sequentially referred to for n sets of the table. The pulse output unit is controlled, and the pulse output from the pulse output unit with the duty ratio controlled to a value other than 50% is input to the pulse counter, and when the pulse reaches the target value, the pulse is interrupted by the coincidence interrupt signal from the pulse counter. By starting the process and switching the output pulse frequency with reference to the next data in the process, the frequency of the output pulse motor to the DC motor driver is controlled, and the drive of the DC motor is controlled.

According to a fourth aspect of the present invention, the frequency data and the target value data set in the operation memory area in advance by the user program are set as one set, and the set of the frequency data and the target value data are continuously set for n sets with reference to the table set. The output unit is controlled, the pulse output from the pulse output unit is input to the pulse counter, and when the pulse reaches the target value, the interrupt processing is started by the coincidence interrupt signal from the pulse counter, and the next data By switching the frequency of the output pulse with reference to, the frequency of the output pulse motor to the pulse motor driver is controlled, and the drive of the pulse motor is controlled.

According to a fifth aspect of the present invention, a plurality of types of internal clocks are provided, which can be selected by software using a multiplexer, and the frequency range of pulse output is widened, so that the range of application can be further expanded.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 2 shows a configuration of a programmable controller A, which includes a CPU 1, a high-speed pulse counter (hereinafter referred to as HSC) 2 and a pulse output unit 3, a ROM 4,
It comprises a RAM 5, an I / O interface 6, and the like.

FIG. 3 is a block diagram of the HSC 2, wherein a dedicated count register 21 for counting a high-speed pulse train of an external single-phase or two-phase or the like, and the count register 21
And a target value register 22 having a function of generating a match interrupt signal to the CPU 1 when the values match.
2 are configured. The target value register 22 can read and rewrite data by software.
The target value data taken into the target value register 22 is the rotation angle (rotational position) of the pulse motor.

FIG. 4 shows a block diagram of the pulse output unit 3, and a count register 3 for counting an internal clock.
The pulse output unit 3 is composed of 1 and a comparison register 32 that outputs a coincidence signal when the value coincides with the count register 31 and an output control circuit 33 that inverts the output for each coincidence by the coincidence signal from the comparison register 32. ing. Frequency data is taken into the comparison register 32, and the comparison register 32 is provided so that the actual frequency is obtained by the frequency data and the number of internal clocks. An output pulse of a shape is output.

FIG. 5A shows the configuration of a table to be used. The frequency data and the target value data of the HSC 2 set in the operation memory area in advance by the user program are stored in one table.
A set is set in the table continuously for n sets. FIG. 5B shows the structure of the instruction, F indicates the symbol of the applied instruction, m indicates the number of the applied instruction, and control is performed with the memory area designated by S as the head of the table.

FIG. 1 is an overall block diagram in which a pulse output unit 3 of a programmable controller A controls the driving of a pulse motor 8 via a pulse motor driver 7. The pulse from the pulse output unit 3 is
The data is input to the count register 21 of the HSC 2, counted, and compared with the target value register 22. Next, the operation will be described. FIG. 6 is a flowchart at the time of instruction operation, and FIG.
Respectively shows a flowchart at the time of interrupt processing.
FIG. 8 shows the relationship between the target value of HSC2 and the pulse output frequency during actual operation.

First, as shown in FIG.
Then, the CPU 1 captures the initial frequency data of the table S, and sets the frequency data in the comparison register 32 of the pulse output unit 3. Further, the target value 1 of the table S is fetched, and the data of the target value 1 is set in the target value register 22 of the HSC2. And
A signal is input from the pulse output unit 3 to the pulse motor driver 7, and the pulse motor driver 7 drives the pulse motor 8. At the same time, the pulse from the pulse output unit 3 is externally or internally connected to the count register 21 of the HSC 2.
When the count value of the count register 21 matches the target value register 22, the HSC2
Input a match interrupt signal to the CPU 1.

When a match interrupt signal is generated, the CPU 1
Captures the next frequency data and target value data in the table. FIG. 7 shows an interrupt process at the target value K. That is, when a coincidence interrupt signal is generated at the target value K,
The CPU 1 fetches the next frequency data K + 1, and if the frequency data is 0, the pulse motor 8 stops. If not, the frequency data K + 1 is set in the comparison register 32 of the pulse output unit 3.

The CPU 1 fetches the next target value K + 1 and sets it in the count register 21 of the HSC 2.
As shown in FIG. 8, this control is continuously performed up to the stop target value. The forward and reverse signals of the pulse motor 8 are switched by turning on and off the forward and reverse signals.

(Embodiment 2) FIG. 9 shows an embodiment 2. In the previous embodiment, one pulse output unit 3 was provided. A flag for controlling the pulse output unit 3a or controlling the pulse output unit 3b is provided so that the pulse output unit is controlled separately during the command operation.

Therefore, in the above embodiment, the forward and reverse rotation signals of the pulse motor are switched by turning on and off the forward and reverse signals. However, in this embodiment, two pulse output units 3 are provided. , And can be output by discriminating them according to an instruction, and the pulse motor driver 7 of a two-pulse input type of forward rotation and reverse rotation pulses can also be controlled.

(Embodiment 3) The overall configuration of the programmable controller A is the same as the configuration shown in FIG. 2, and the high-speed pulse counter 2 is also the same as the configuration shown in FIG. The target value register 22 in the HSC 2 is the same as that in the first embodiment.
Similarly to the above, data can be read and rewritten by software. The target value data taken into the target value register 22 is the rotation angle (rotational position) of the DC motor.

FIG. 11 shows a block diagram of the pulse output unit 3, and a count register 3 for counting an internal clock.
1 and two comparison registers 32A and 32B that output a coincidence signal when the value coincides with the count register 31, and an output control circuit 33 that inverts the output for each coincidence by the two coincidence signals. It is configured.

The comparison register 32A receives frequency data, and is provided with a comparison register 32A so that the actual frequency is obtained by the frequency data and the number of internal clocks. A coincidence signal is input to the count register 31 as a reset signal. It has become so. The comparison register 32B is set to a value smaller than that of the comparison register 32A, and the two coincidence signals divide the frequency of the internal clock by the output control circuit 33 to output an output pulse in a duty-controlled form. ing.

FIG. 1 shows the operation of the pulse output unit 3.
As shown in FIG. 2, when the set value of the comparison register 32B is set to exactly half the value of the comparison register 32A, a pulse output with a duty ratio of 50% becomes possible. The frequency of the pulse output can be changed by changing the set value of the comparison register 32A. The duty ratio of the pulse output can be changed by changing the set value of the comparison register 32B.

FIG. 13A shows the configuration of a table to be used. The duty data set in the operation memory area and the target value data of the HSC2 are set as one set by the user program in advance, and the set is continuously set for n sets. And then set it on the table. FIG. 13B shows the structure of the instruction.
Indicates the symbol of the application instruction, m indicates the number of the application instruction, and control is performed with the memory area designated by S as the head of the table.

FIG. 10 is an overall block diagram in which a DC output is provided by the pulse output unit 3 of the programmable controller A.
The drive of the motor 9 is controlled. The amount of rotation of the DC motor 9 is input to the count register 21 of the HSC 2 via the encoder 10, counted, and compared with the target value register 22. Next, the operation will be described. FIG.
Shows a flowchart at the time of instruction operation, and FIG. 15 shows a flowchart at the time of interrupt processing. The relationship between the target value of HSC2 and the pulse output frequency during the actual operation is the same as that of FIG. 8 of the first embodiment.

First, as shown in FIG. 14, when the execution condition a becomes 1 and rises, the frequency data of the table S is fetched by the CPU 1, the frequency data is set in the comparison register 32A of the pulse output unit 3, and The duty designation data is fetched and set in the comparison register 32B of the pulse output unit 3. Also, the target value 1 of the table S
And the data of the target value 1 is set in the target value register 22 of the HSC2.

Then, a signal is input from the pulse output unit 3 to the DC motor 9, and the amount of rotation of the DC motor 9 is input to the count register 21 of the HSC 2 via the encoder 10. When HSC2 matches the target value register 22,
A match interrupt signal is input to PU1. When a coincidence interrupt signal is generated, the CPU 1 fetches the next duty data and target value data in the table. FIG. 15 shows an interrupt process at the target value K. That is, when the coincidence interrupt signal is generated at the target value K, the CPU 1 fetches the next duty data K + 1, and stops the pulse output if the duty data is 0, but stops the pulse output if the duty data is not 0. The numerical value based on this is set in the comparison register 32B of the pulse output unit 3.

The CPU 1 fetches the next target value K + 1 and sets it in the count register 21 of the HSC 2.
This control is continuously performed up to the target stop value (FIG. 8). As described above, the duty data and the target value data set in the operation memory area in advance by the user program are set as one set, and the pulse output unit 3 is controlled by referring to the set table continuously for n sets. Then, the DC motor 9 is driven by the pulse output from the pulse output unit 3 and the pulse from the encoder 10 connected thereto is transmitted to the HSC2.
When the target value is reached, the interrupt processing is started by the coincidence interrupt signal from the HSC2, and the duty of the output pulse is switched by referring to the next data in the interrupt processing. 9 controls the duty of the output pulse to the DC motor 9 and controls the drive of the DC motor 9. Therefore, the duty of the output pulse and the number of pulses are controlled while simultaneously controlling the HSC 2 and the pulse output unit 3. This makes it possible to drive the DC motor 9 at low cost without requiring separate analog output hardware.

Further, the pulse output duty can be switched at an arbitrary number of pulses of the user by the instruction of the CPU 1 and the interrupt processing, so that any speed control and position control can be performed. It becomes. Further, in the present embodiment, the same contents as those in the first embodiment can be realized. In other words, the duty ratio is always 50
%, And only pulse frequency control is performed to drive the pulse motor.

(Embodiment 4) The configuration of the entire programmable controller A is the same as the configuration shown in FIGS. 1 and 2, and the high-speed pulse counter 2 is also the same as the configuration shown in FIG. Therefore, the function of HSC2 is the same as that of the first embodiment. Further, the configuration of the pulse output unit 3 shown in FIG. 16 is the same as that of the third embodiment shown in FIG.
A and 32B are for frequency control, respectively. That is, as shown in FIG. 16, a count register 31 that counts an internal clock and comparison registers 32A and 32B that output a match signal when the value matches the count register 31.
The pulse output unit 3 includes an output control circuit 33 that inverts the output for each match according to the two match signals.

The comparison registers 32A and 32B receive frequency data, and the comparison register 32B is set to a value that is １ ／ of the content of the comparison register 32A. Comparison registers 32A and 32B are provided so that the actual frequency is obtained by the frequency data and the number of internal clocks, and the output control circuit 33 outputs an output pulse in which a match signal is obtained by dividing the internal clock. It has become.

The structure of the table used and the structure of the instruction are the same as those in FIG. Next, the operation will be described. FIG. 17 is a flowchart at the time of instruction operation, and FIG. 18 is a flowchart at the time of interrupt processing. The relationship between the target value of HSC2 and the pulse output frequency during the actual operation is the same as that of FIG. 8 of the first embodiment.

First, as shown in FIG. 17, when the execution condition a becomes 1 and rises, the initial frequency data of the table S is fetched by the CPU 1 and the frequency data is set in the comparison register 32A of the pulse output unit 3. A value that is １ ／ of the set value of the comparison register 32A is set in the comparison register 32B. Further, the target value 1 of the table S is fetched, and the data of the target value 1 is set in the target value register 22 of the HSC2.

Then, a signal is input from the pulse output unit 3 to the pulse motor driver 7, and the pulse motor driver 7 drives the pulse motor 8. At the same time, since the pulse from the pulse output unit 3 is also input to the count register 21 of the HSC 2 via an external or internal connection, when the count value of the count register 21 matches the target value register 22, the coincidence division from the HSC 2 to the CPU 1 is performed. Input signal.

When a coincidence interrupt signal is generated, the CPU 1
Captures the next frequency data and target value data in the table. FIG. 18 shows an interrupt process at the target value K.
That is, when a coincidence interrupt signal is generated at the target value K, the CPU 1 fetches the next frequency data K + 1, and if the frequency data is 0, the pulse motor 8 stops.
If it is not 0, the frequency data K + 1 is set in the comparison register 32A of the pulse output unit 3, and a half of the set value of the comparison register 32A is set in the comparison register 32B.

The CPU 1 fetches the next target value K + 1 and sets it in the count register 21 of the HSC 2.
As shown in FIG. 8, this control is continuously performed up to the stop target value. The forward and reverse signals of the pulse motor 8 are switched by turning on and off the forward and reverse signals.

Further, in this embodiment, the forward rotation and the reverse rotation of the pulse motor may be performed by the structure as shown in FIG. As described above, in the present embodiment, the frequency data and the target value data set in the operation memory area in advance by the user program are set as one set, and the pulse output is performed while referring to the table continuously set for n sets. The pulse output from the pulse output unit is input to the pulse counter 2, and when the pulse reaches the target value, the interrupt processing is started by the coincidence interrupt signal from the pulse counter 2, and the next interrupt is executed. By switching the frequency of the output pulse with reference to the data, the frequency of the output pulse to the pulse motor driver 7 is controlled and the driving of the pulse motor 8 is controlled. It is possible to control the pulse output frequency and the number of pulses while simultaneously controlling the pulse output unit 3 and separately output the pulse. Without the need of hardware, in which can be performed inexpensively pulse motor drive.

Further, the pulse output frequency can be switched at an arbitrary number of pulses of the user by the instruction of the CPU 1 and the interrupt processing, so that any speed control can be handled. Further, with the configuration of the present embodiment, the duty control is performed in the same manner as in the third embodiment,
The speed and position of the DC motor can be controlled, and an inexpensive and multifunctional programmable controller can be provided.

(Embodiment 5) FIG. 19 shows Embodiment 5 in which a selection circuit 11 is added to the pulse output unit 3 of Embodiment 1 to extend the range of the output frequency. That is, if the internal system clock is f, f / 1
The divided outputs of 6, f / 32, f / 64, and f / 128 are selected by the multiplexer 12, and the output is input to the count register 31 as a clock. In this embodiment, there are four types of frequency division outputs, but any number may be used.

The selection circuit 11 is controlled by software.
Can be selected, the frequency range of the pulse output can be expanded, and the application range can be further expanded. FIG. 20 shows the configuration of a table corresponding to FIG. 5 of the first embodiment, and has a form in which an address 0 is added to FIG. FIG. 21 is a flowchart at the time of an instruction operation, which is different from FIG. 6 of the first embodiment in that a processing portion next to the branch is added.

Next, FIG. 22 shows the relationship between the frequency of the output pulse and the comparison register 32 in this embodiment. FIG.
As shown in (1), if the frequency of the input clock of the pulse output unit 3 is one, only one pattern shown in FIG. 22 can be output, so that the usable frequency band is narrowed and the application is limited. However, in this embodiment, the pulse output unit 3
Is provided with a selection circuit 11 capable of selecting an input clock.
Since this can be selected by an instruction, usable frequencies are widened, and an application range can be widened.

[0046]

As described above, the present invention provides a pulse counter comprising a count register for counting a pulse train from the outside, a target value register for generating a coincidence interrupt signal when a value coincides with the count register, and an internal clock. A pulse output unit comprising: a count register for counting the count; a comparison register for outputting a match signal when the value matches the count register; The frequency data set in the operation memory area in advance by the user program and set in the comparison register of the pulse output unit and the target value data set in the target value register of the pulse counter are set as one set, and are continuously set for n sets. The pulse output unit is controlled while referring to the set table, Interrupt processing is performed by a match interrupt signal from the pulse counter that is generated when the number of pulses input to the count register of the pulse counter from the output unit matches the value of the target value register. Since the CPU is configured to switch to and set to value data, the frequency data and target value data previously set in the operation memory area by the user program are set as one set, and the set is continuously set for n sets. Control the pulse output unit while referring to the table
The pulse output from the pulse output unit is input to the pulse counter, and when the pulse reaches the target value, the interrupt processing is started by the coincidence interrupt signal from the pulse counter. By switching the pulse frequency, the frequency of the output pulse to the pulse motor driver is controlled, and the pulse motor is driven and controlled.Thus, while simultaneously controlling the pulse counter and the pulse output unit, The pulse output frequency and the number of pulses can be controlled, and pulse motor drive can be performed at low cost without the need for separate pulse output hardware. Also, pulse output can be performed by CPU instructions and interrupt processing. It is possible to switch the frequency at the point of the user's arbitrary number of pulses. To the control in which exhibits the it is possible to cope effectively.

According to a second aspect of the present invention, a pulse counter comprising a count register for counting a pulse train from the outside, a target value register for generating a coincidence interrupt signal when a value coincides with the count register, and an internal clock are counted. A count register, a comparison register that outputs a match signal when the value matches the count register, an output control circuit that inverts the output by the match signal, outputs a pulse with a duty ratio controlled to 50%, and inputs the pulse to a pulse motor driver And a frequency data set in a calculation memory area in advance by a user program and set in a comparison register of the pulse output unit and a target value data set in a target value register of the pulse counter.
The pulse output unit is controlled while referring to a table that is set continuously for n sets, and the number of pulses input from the pulse output unit to the count register of the pulse counter matches the value of the target value register. The interrupt processing is performed by the coincidence interrupt signal from the pulse counter that is generated at the time of the operation, and the CPU switches to the next frequency data and target value data in the table and sets them. The frequency data and target value data set in the memory area are set as one set,
The pulse output unit is controlled while referring to a table set continuously for n sets, and the pulse output from the pulse output unit with the duty ratio controlled to 50% is input to the pulse counter, and the target value is set. , The interrupt process is started by the coincidence interrupt signal from the pulse counter, and the output pulse frequency is switched to the pulse motor driver by switching the frequency of the output pulse by referring to the next data in it. Control the pulse motor and control the pulse motor, so that the pulse output frequency and the number of pulses can be controlled while simultaneously controlling the pulse counter and the pulse output unit. Pulse motor drive can be performed at low cost without the need for output hardware.
The pulse output frequency can be switched at the point of the user's arbitrary number of pulses by the CPU command and interrupt processing, so that any speed control and position control can be supported. It is.

According to a third aspect of the present invention, there is provided a pulse register comprising a count register for counting a pulse train from the outside, a target value register for generating a coincidence interrupt signal when a value coincides with the count register, and a count register for counting an internal clock. A comparison register for outputting a coincidence signal when the value coincides with the count register; an output control circuit for inverting the output by the coincidence signal to output a pulse whose duty ratio is controlled to other than 50% and inputting the pulse to the DC motor driver; And a set of the frequency data set in the operation memory area in advance by the user program and set in the comparison register of the pulse output unit and the target value data set in the target value register of the pulse counter. While referring to the table set continuously for the set, The pulse output unit is controlled, and the interrupt processing is performed by a match interrupt signal from the pulse counter generated when the number of pulses input to the count register of the pulse counter from the pulse output unit matches the value of the target value register. It is composed of a CPU that switches and sets the next frequency data and target value data in the table.
A set of frequency data and target value data set in the operation memory area in advance by a user program is set, and the pulse output unit is controlled while referring to a table that is continuously set for n sets. When the duty ratio is controlled to a value other than 50%, the output pulse is input to the pulse counter. When the pulse reaches the target value, the interrupt processing is started by the coincidence interrupt signal from the pulse counter, and the next data is output. , By controlling the frequency of the output pulse motor to the DC motor driver by switching the frequency of the output pulse, and by controlling the drive of the DC motor, speed control and position control can be arbitrarily performed. Things.

Further, a pulse counter comprising a count register for counting a pulse train from the outside, a target value register for generating a coincidence interrupt signal when a value coincides with the count register, and an internal clock are counted. A count register, two comparison registers for outputting a coincidence signal when the value matches the count register, and an output control circuit for inverting the output according to the coincidence signal from the two comparison registers, outputting a pulse, and inputting the pulse to the pulse motor driver. Pulse output unit, frequency data set in the operation memory area in advance by the user program and set in the comparison register of the pulse output unit and target value data set in the target value register of the pulse counter are set to 1
The pulse output unit is controlled while referring to a table that is set continuously for n sets, and the number of pulses input from the pulse output unit to the count register of the pulse counter matches the value of the target value register. The interrupt processing is performed by the coincidence interrupt signal from the pulse counter that is generated at the time of the operation, and the CPU switches to the next frequency data and target value data in the table and sets them. The frequency data and target value data set in the memory area are set as one set,
The pulse output unit is controlled while referring to a table set for n sets continuously, and the pulse output from the pulse output unit is input to the pulse counter. The interrupt process is started by the interrupt signal, and the frequency of the output pulse is switched to the pulse motor driver by switching the frequency of the output pulse by referring to the next data in the interrupt process. By controlling the drive,
Speed control and position control can be arbitrarily performed.

According to a fifth aspect of the present invention, since a plurality of types of internal clocks input to the count register are provided and a multiplexer is provided for an arbitrary internal clock, a plurality of types of internal clocks are provided. The range of application can be further expanded by expanding the frequency range of the pulse output as selectable by the software according to (1).

[Brief description of the drawings]

FIG. 1 is an overall block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a programmable controller.

FIG. 3 is a block diagram of a pulse counter.

FIG. 4 is a block diagram of a pulse output unit.

FIG. 5 is an explanatory diagram of the above.

FIG. 6 is a diagram showing a flowchart at the time of an instruction operation.

FIG. 7 is a diagram showing a flowchart at the time of interrupt processing.

FIG. 8 is a diagram illustrating a relationship between an HSC target value and a pulse output frequency during an actual operation.

FIG. 9 is a block diagram of a second embodiment.

FIG. 10 is an overall block diagram of a third embodiment.

FIG. 11 is a block diagram of a pulse output unit.

FIG. 12 is an operation waveform diagram of the pulse output unit.

FIG. 13 is an explanatory diagram of the above.

FIG. 14 is a diagram showing a flowchart at the time of an instruction operation.

FIG. 15 is a diagram showing a flowchart at the time of interrupt processing.

FIG. 16 is a block diagram of a pulse output unit according to a fourth embodiment.

FIG. 17 is a diagram showing a flowchart at the time of an instruction operation.

FIG. 18 is a diagram showing a flowchart at the time of interrupt processing.

FIG. 19 is a block diagram of a pulse output unit according to the fifth embodiment.

FIG. 20 is a configuration diagram of a table used.

FIG. 21 is a diagram showing a flowchart at the time of an instruction operation.

FIG. 22 is a diagram illustrating a relationship between the frequency of an output pulse and a comparison register.

[Explanation of symbols]

 1 CPU 2 High-speed pulse counter (HSC) 3 Pulse output unit 7 Pulse motor driver 8 Pulse motor 21 Count register 22 Target value register 31 Count register 32 Comparison register 33 Output control circuit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G05D 3/12 305 H02P 8/14

Claims (5)

(57) [Claims] 1. A pulse counter comprising a count register for counting an external pulse train, a target value register for generating a coincidence interrupt signal when a value of the count register coincides with the count register, a count register for counting an internal clock, and a count register A pulse output unit consisting of a comparison register that outputs a coincidence signal when the value matches the value, an output control circuit that inverts the output according to the coincidence signal, outputs a pulse, and inputs the pulse to the pulse motor driver. The frequency data set in the memory area and set in the comparison register of the pulse output unit and the target value data set in the target value register of the pulse counter are 1
The pulse output unit is controlled while referring to a table that is set continuously for n sets, and the number of pulses input from the pulse output unit to the count register of the pulse counter matches the value of the target value register. A programmable controller comprising: a CPU that performs interrupt processing with a coincidence interrupt signal from a pulse counter that is generated when switching to the next frequency data and target value data in a table and sets the CPU. 2. A pulse counter comprising a count register for counting a pulse train from the outside, a target value register for generating a coincidence interrupt signal when a value coincides with the count register, a count register for counting an internal clock, and a count register A pulse output comprising a comparison register for outputting a coincidence signal when the value and the output signal coincide with each other, and an output control circuit for inverting the output by the coincidence signal to output a pulse whose duty ratio is controlled to 50% and inputting the pulse to a pulse motor driver. And the frequency data set in the operation memory area in advance by the user program and set in the comparison register of the pulse output unit and the target value data set in the target value register of the pulse counter are set as one set. Controls the pulse output unit while referring to the table set When the number of pulses input from the pulse output unit to the count register of the pulse counter matches the value of the target value register, interrupt processing is performed with a match interrupt signal from the pulse counter that is generated. A programmable controller, comprising: a CPU that switches and sets data and target value data. 3. A pulse counter comprising a count register for counting an external pulse train, a target value register for generating a coincidence interrupt signal when a value of the count register coincides with the count register, a count register for counting an internal clock, and a count register. A comparison register that outputs a coincidence signal when the values match, and an output control circuit that inverts the output according to the coincidence signal, outputs a pulse whose duty ratio is controlled to a value other than 50%, and inputs the pulse to a DC motor driver. The output unit and the frequency data set in the operation memory area in advance by the user program and set in the comparison register of the pulse output unit and the target value data set in the target value register of the pulse counter are set as one set. The pulse output section is controlled while referring to the table set When the number of pulses input from the pulse output unit to the count register of the pulse counter matches the value of the target value register, interrupt processing is performed with a match interrupt signal from the pulse counter that is generated. A programmable controller, comprising: a CPU that switches and sets frequency data and target value data. 4. A pulse counter comprising a count register for counting a pulse train from the outside, a target value register for generating a coincidence interrupt signal when a value coincides with the count register, a count register for counting an internal clock, and a count register A pulse output unit comprising: two comparison registers for outputting a coincidence signal when the values coincide with each other; an output control circuit for inverting the output by a coincidence signal from the two comparison registers to output a pulse and inputting the pulse to a pulse motor driver The frequency data set in the operation memory area in advance by the user program and set in the comparison register of the pulse output unit and the target value data set in the target value register of the pulse counter are set as one set, and are continuously set for n sets. The pulse output unit while referring to the table When the number of pulses input from the pulse output unit to the count register of the pulse counter matches the value of the target value register, interrupt processing is performed with a match interrupt signal from the pulse counter that is generated. A programmable controller, comprising: a CPU that switches and sets data and target value data. 5. The programmable controller according to claim 1, wherein a plurality of types of internal clocks input to the count register are provided, and a multiplexer for selecting an arbitrary internal clock is provided.