JPH05328734A - Microcomputer having built-in motor control circuit - Google Patents

Abstract

PURPOSE:To lighten the load on CPU execution processing, and to carry out control in realtime by eliminating the need for setting at every interruption while setting the interruption of a CPU at every several time by automatically inverting the start level of a PWM waveform by hardware. CONSTITUTION:When data are set previously to the reload register 15c and reload register 25d of one-shot timer 5bU at the same time at the time of an automatic mode, data are transferred alternately from each reload register 15c and 25d to the one-shot timer 5bU by a selector 5s when the content of the one-shot time 5bU reaches '0000H'. When '1' is written to the bit b5 of a waveform output mode register and the one-shot timer 5bU is operated, a three-phase waveform output mode is operated, and the content of an automatic output polarity setting flip-flop 5g is set to an output polarity setting toggle flip-flop 5k.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention mainly relates to a microcomputer incorporating a motor control circuit for controlling a three-phase inverter motor.

[0002]

2. Description of the Related Art Conventionally, in the case of controlling an AC motor, mainly a three-phase inverter motor, using a microcomputer, a configuration as shown in FIGS. 17 and 18 has been adopted.

FIG. 17 is a block diagram showing a circuit configuration for controlling a three-phase inverter motor. In FIG. 17, reference numeral
Reference numeral 501 denotes a microcomputer, which includes a CPU, a storage device such as ROM, RAM, a timer, and a clock oscillator. It should be noted that this microcomputer 501 can also be configured with one chip.

Reference numeral 502 denotes an additional circuit, which is composed of a pulse width modulation (hereinafter referred to as PWM) signal generated by the microcomputer 501.
Converts PWM output waveform to inverter output waveform. As a result, U, #U, V, #V, W, #W (#
Indicates an inverted signal, and a three-phase inverter waveform consisting of three phases is obtained, and this is given to a motor (not shown) as a motor drive signal.

As an actual device, as shown in FIG. 18, a microcomputer 501 is mounted on a printed circuit board 503.
It is used as a motor control unit that implements and the additional circuit 502.

However, when the configuration shown in FIG. 17 is adopted, an additional circuit is required in addition to the microcomputer, and the printed circuit board 50 as shown in FIG.
When mounting on top of 3, there is a problem that the mounting area becomes large and it is easily affected by external noise. Furthermore,
There is also a problem that the cost increases because an additional circuit including various components other than the microcomputer is required.

In view of such circumstances, the inventors of the present application have previously proposed the invention disclosed in Japanese Patent Laid-Open No. 3-70475.

The invention disclosed in Japanese Laid-Open Patent Publication No. 3-70475 has a CPU 501a, a RAM 501b, a ROM 501c, an oscillator 501d, a timer as shown in the block diagram of FIG.
501e, motor control circuit 504 and the like are configured as one microcomputer 501 on one chip. By adopting such a configuration, it is intended to solve the problems that the mounting area becomes large and that it is easily affected by external noise, as seen in the above-mentioned conventional example.

Also, for example, "FIN" issued by Fujitsu Limited
D ”Vol. 9 No. 2 (March 1991) discloses a microcomputer for controlling an AC motor. This microcomputer will be described below as a conventional example.

FIG. 1 is a block diagram showing the configuration of the above-mentioned conventional microcomputer. In FIG. 1, reference numeral 1a is a CPU (central processing unit), 1b is a RAM,
1c is a ROM, 1d is an oscillator, 1e is a general-purpose port, 1f and
1g is an interrupt control circuit, 1h is a watchdog timer, 1i is a timer unit, 1j is an 8-bit reload timer, 1k is a PWM timer module, 1l is an AD converter, 1m is a UART, and 1n is The I / O expansion serial interfaces are respectively shown, and these are connected to each other by an internal bus 1o and are configured on the same chip as a one-chip microcomputer.

FIG. 2 shows the timer unit 1i shown in FIG.
3 is a block diagram showing the configuration of FIG. In FIG. 2, reference numerals 2a to 2c denote output compare registers 0 to 3 and 2f, respectively.
2i is a compare buffer register 0 to 3, 2j is a timer counter, 2k is a timer control register, 2l is a timer interrupt control register, and 2m is a compare register.

FIG. 3 is a block diagram showing the structure of the 8-bit reload timer 1j shown in FIG. This timer 1j
Functions as a short-circuit prevention timer (hereinafter, abbreviated as dead time timer) as described later. In FIG. 3, reference numerals
3a is a timer control register, 3b is a timer data buffer, 3c is a flip-flop, 3d is a port selector, 3e
Indicates an 8-bit reload timer.

FIG. 4 is a block diagram in which the dead time timer shown in FIG. 3 and the timer unit shown in FIG. 2 are combined.

In FIG. 4, reference numeral 4a on the timer unit side is a 16-bit timer (timer counter 2j in FIG. 2).
4b is a U-phase compare buffer (corresponding to compare buffer register 0 2f in FIG. 2), 4c is a V-phase compare buffer (corresponding to compare buffer register 1 2g in FIG. 2), and 4d is a W-phase compare buffer. A buffer (corresponding to the compare buffer register 22h in FIG. 2), 4e is a cycle setting compare register (corresponding to the compare buffer register 32i in FIG. 2), and 4f to 4i are output compare registers 0 to 3.
(Corresponding to output compare registers 0 2a to 32d in Fig. 2), 4j is a data buffer, and 4o is a compare register.
(Corresponding to the compare register 2m in FIG. 2).

Reference numeral 4k on the dead time timer side
Is a timer data buffer (the timer data buffer in FIG. 3
3b), 4l a dead time timer (corresponding to the 8-bit reload timer in Figure 3), and 4m a flip-flop.
(Corresponding to 3c in FIG. 3) and 4n indicate a port selector (corresponding to 3d in FIG. 3). In FIG. 4, reference symbols RTO0 to RTO5 indicate output ports of each phase.

FIG. 13 shows the AD converter 1l shown in FIG.
3 is a block diagram showing the configuration of FIG. In FIG. 13, reference numeral 13a is a selector, 13b is an AD mode register, 1
3c is a comparator, 13d is a resistance ladder, 13e is AD
The conversion data buffer and the decoder 13f are shown.

Next, the operation of the conventional AC motor control microcomputer having the above-mentioned configuration will be described.

First, the cycle setting compare register 4e
The PWM cycle is set in (compare buffer register 3 2i). The content set in the cycle setting compare register 4e (compare buffer register 3 2i) is the content of the timer 4a (timer counter 2j) is "0000H" (H represents a hexadecimal number).
Then, it is transferred to the output compare register 3 4i (output compare register 3 2d). At the same time, the content of timer 4a (timer counter 2j) is "0000H".
Then, an interrupt is generated in CPU 1a, and the interrupt processing updates the data in cycle setting compare register 4e (compare buffer register 32i).

On the other hand, the change timing of the PWM waveform is set in the U-phase compare buffer 4b (compare buffer register 02f). The contents set in the U-phase compare buffer 4b (compare buffer register 0 2f) are stored in timer 4a.
When the content of (timer counter 2j) reaches "0000H", it is transferred to and held in output compare register 3 4i (output compare register 0 2a). Then, the value of timer 4a (timer counter 2j) and output compare register 3 4i (output compare register 0 2a)
When the value held by is the same value, the corresponding port, in this case the output ports RTO0 and
The output level of RTO3 is inverted.

The data used by these compare buffer registers and the like are the AD converter 1l and the measurement timer (timer unit 1i) built in the microcomputer.
Etc.) is often used. A-D
The converter 1l converts the analog input value from the outside into a digital value and compares it with the compare buffer registers 2f, 2g, 2h, 2i.
It is used for comparison data of register values such as, or calculation data for obtaining register values.

The operation of the conventional AD converter is shown in FIG.
As shown in 13, analog input pins AN0 to AN4
When performing AD conversion of 5 inputs, analog input terminals AN0 to AN4 are used as shown in the schematic diagram of FIG. 11 regardless of the required sampling cycle for analog input information.
Were repeatedly repeated evenly and sampled in order.

[0022]

Since the conventional microcomputer with a built-in motor control circuit is configured as described above, it is necessary to arbitrarily change the contents of the start level of the PWM output waveform for each cycle, and the timer data or If you want to change the frequency of the clock, you usually have to rewrite the variables by interrupting the program running on the CPU. Therefore, if these data are rewritten, the load on the CPU will increase. Further, when controlling a high-frequency inverter waveform, there is a possibility that the processing speed of the CPU cannot keep up with the situation and the data cannot be updated in real time.

Further, in the AD converter used in the conventional microcomputer with a built-in motor control circuit, the operation of changing the sampling cycle for each analog input information according to the required frequency is not performed. Because of unnecessary sampling, A
-The sampling time for D conversion is longer overall.
When the AD conversion value obtained in this way is used for PWM output data or the like, the AD conversion sampling cycle is constant regardless of the frequency of use, and therefore there is a risk that the data may not be updated in time.

The present invention has been made in view of the above problems, and in the case of inverting the contents of the start level of the PWM output waveform for each cycle, a program executing the necessary variables on the CPU The setting is made so that the contents of the start level are automatically inverted every cycle and the setting for each interrupt is unnecessary. Furthermore, when changing timer data or clock frequency, variables are usually rewritten by interrupt processing of the program running on the CPU, but data rewriting performed each time these interrupt processing are performed. An object of the present invention is to provide a microcomputer with a built-in motor control circuit that can be set every other time.

In consideration of the application example, on the contrary, there is a case where it is not necessary to rewrite the above-mentioned data by interrupt processing, but in such a case, a motor control circuit having an interrupt timing control capable of controlling is also built-in. It also aims to provide a microcomputer.

Further, it is another object of the present invention to provide a microcomputer with a built-in motor control circuit capable of changing the sampling cycle of analog input information according to the required frequency of each information.

[0027]

A microcomputer with a built-in motor control circuit according to the present invention is capable of automatically inverting the start level of a PWM output or changing the start level according to an arbitrary setting pattern. A circuit, an interrupt request control circuit for controlling the timing of interrupts, and a multifunction reload register are configured as additional functions.

Further, the AD converter is constructed so that a plurality of sampling periods can be set for the analog input information.

Further, by adding a DMAC (Direct Memory Access Controller), the load on the CPU, which was required to set the timer data at the time of interruption, can be reduced to zero.

[0030]

In the microcomputer with a built-in motor control circuit according to the present invention, the rise generation means of the timer for each phase of the motor control signal outputs a rise pulse in response to the clock from the clock generation means, and based on this rise pulse, three three-phase An inverter waveform generation timer produces an output. Next, the register set with a predetermined value by the CPU determines the start level of the three-phase inverter waveform generation timer, and the start level setting signal is obtained from the logical product of the rising pulse and the start level. And a three-phase inverter waveform is generated by the flip-flop circuit from each output pulse.
At this time, the start level is inverted every rising pulse.

In the microcomputer incorporating the three-phase inverter motor controller according to the present invention, an interrupt is generated when the rising generation means outputs a rising pulse by the clock from the clock generation means. The timing is controlled such that the interrupt is generated once every rising pulse and every three times.

Further, when data is set during triangular wave modulation of the three-phase inverter PWM waveform, the cycle of the three-phase inverter PWM waveform corresponds to two PWM cycles of the microcomputer. In this case, the PWM data of the microcomputer corresponding to the triangular wave modulation of the three-phase inverter PWM waveform is set so that the data of the first cycle and the data of the second cycle are the target for the PWM cycle. For example, three-phase inverter PWM
If the period of the triangular wave modulation of the waveform is 100, the PWM period of the microcomputer is 50, and if the PWM data of the first period is set to 10, the PWM data of the second period is set to 40.

In the case of changing the timer data or the like for outputting the PWM waveform which requires such a method, conventionally, only the data of the next cycle was set in one interrupt process for updating the data. In the microcomputer with a built-in motor control circuit according to the present invention, by adding a reload register, data for two cycles can be set at the same time by one interrupt processing. Further, by adding the function of inverting the set data, it is possible to set the target data for the cycle with one data setting.

By setting the data of the first cycle, the reload register is used to change the PWM cycle data to 1
By adding a circuit that subtracts the data of the second cycle and calculates the data of the second cycle, the target data can be set at once for the cycle.

Further, in the AD converter of the microcomputer with a built-in motor control circuit according to the present invention, the selector and the decoder are improved so that the analog input information can correspond to a plurality of sampling periods. Therefore, the decoder selects the analog input terminal at two kinds of sampling periods set by the register, and therefore, for example, the analog input terminals AN0, AN1
Is used frequently, and analog input terminals AN3 to AN4 are used less frequently.When performing AD conversion of analog input terminals AN0 to AN4, analog input terminals AN0 to AN4 are as shown in the schematic diagram of Fig. 12. AD conversion can be performed in order.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments.

First, the three-phase inverter of one embodiment of the microcomputer with built-in motor control circuit of the present invention will be described.
The output operation of the PWM waveform will be described with reference to FIG. In addition,
FIG. 5 is a block diagram showing a configuration of a three-phase waveform generating circuit which is a main part of the motor control circuit built-in microcomputer of the present invention.

In FIG. 5, reference numeral 5U is a U phase block for generating a U phase waveform, 5V is a V phase block for generating a V phase waveform, and 5W is a W for generating a W phase waveform. Each of the phase blocks is shown, and basically all have the same configuration. Therefore, in FIG. 5, only the U-phase block 5U is shown with its specific internal structure.

In FIG. 5, reference numeral 5a indicates a period setting timer, and 5bU indicates a U-phase one-shot timer which outputs a pulse using a signal output from the period setting timer 5a as a trigger. The V-phase block 5V and the W-phase block 5W have a one-shot timer 5bU for the U-phase.
A one-shot timer 5bV for V-phase and a one-shot timer 5bW for W-phase having the same structure as the above are respectively provided.

Reference numeral 5c is a one-shot timer 5b.
Reload register 1 for U, 5d one shot timer
The reload register 2 for 5bU is shown respectively. Reference numeral 5e is a flip-flop for setting an interrupt valid polarity, and an interrupt valid polarity bit is input to its D-input terminal. Reference numeral 5f is a flip-flop for setting an interrupt interval, and an interrupt interval setting bit is input to its D- input terminal. 5g is a flip-flop for output polarity selection, and the output polarity selection bit is input to its D-input terminal. 5h is a flip-flop for automatic three-phase mode setting, and the automatic three-phase mode setting bit is input to its D-input terminal.

Reference numeral 5i is an output polarity setting flip-flop, 5j is an output polarity selector, 5k is an output polarity setting toggle flip-flop, 5l is a short circuit prevention time setting timer reload register, and 5m is a short circuit prevention time setting. Timer
(Dead time timer), 5n a dead time flip-flop, 5o1 and 5o2 a logic circuit, 5p1 and 5p2
Is an output buffer, 5q is an "H" level output setting flip-flop, 5r is an output buffer control flip-flop, and 5s is a selector for selectively connecting both reload registers 5c and 5d to the one-shot timer 5bU. Shows.

FIG. 6 is a schematic diagram showing the bit configuration of the waveform output mode register.

This waveform output mode register has bits b0 ...
It has an 8-bit structure up to b7, and in the three-phase waveform mode, the three bits b2, b1, and b0 are set to "100". Then, the bit b3 is given to the flip-flop 5g as the initial value of the automatic output polarity selection bit. Specifically, if the bit b3 is "0", the positive polarity is set, and if the bit b3 is "1", the negative polarity is set. Bit b4 is a flip-flop
It is given to 5h as the setting value of the automatic three-phase mode selection bit. Specifically, if the bit b4 is "0", the three-phase mode is set, and if the bit b4 is "1", the automatic mode is set.

Bit b6 sets the trigger of short-circuit prevention time setting timer 5m. Specifically, if bit b6 is "0", each phase block 5U, 5V, 5W one-shot timer 5bU, 5b
If both edges of the V, 5bW one-shot pulse are "1", the falling edge of each one-shot timer 5bU, 5bV, 5bW one-shot pulse is selected. Further, bit b7 is a flip-flop for controlling the output buffer.
Set the initial value of 5r output. Specifically, bit b7
If is "0", output buffer control flip-flop
Waveform output from 5r is prohibited, and if "1", it is permitted.

With such a waveform output mode register, the three-phase waveform mode using four timers of the one-shot timers 5bU, 5bV, 5bW for each phase and the period setting timer 5a is selected. The bit b5 is undefined.

In the three-phase waveform output mode selected by the above waveform output mode register, the timer mode register is set as shown in the schematic view of FIG. That is, as shown in Fig. 7 (a), each one-shot timer 5bU, 5bV, 5bW is set to the external trigger of the one-shot pulse mode, the rising edge is valid,
As shown in, the period setting timer 5a sets the timer mode in the respective timer mode registers.

In the circuit having the configuration shown in the block diagram of FIG. 5, the positive phase waveform (U
Phase, V-phase, W-phase) and reverse-phase waveform (#U phase, #V phase, port P5 ₅ 6 of waveforms of the U-phase block 5U #W phase), P5 _4, V-phase block 5V of P5 _3, P5 ₂ , W-phase block 5W P5 ₁ , P5 ₀
From "L" level active.

Of the timers used in this three-phase waveform output mode, the one-shot timer 5bU has U-phase and # U-phase waveforms,
The one-shot timer 5bV controls the V-phase and # V-phase waveforms, and the one-shot timer 5bW controls the W-phase and # W-phase waveforms. The period setting timer 5a controls each of these one-shot timers 5b.
The cycle of U, 5bV, 5bW one-shot pulse output is controlled.

In the waveform output, the three-phase waveform output (U
Phase, V phase, W phase) "L" level is the opposite phase waveform output
The short circuit prevention time is set so that it does not overlap with the "L" level of (#U phase, #V phase, #W phase). This short-circuit prevention time is set by three 8-bit short-circuit prevention time setting timers, which are provided in each phase block and share the reload register 5l (see Fig. 5, short-circuit prevention time setting for U-phase block 5U). Although only the timer 5m is shown, the V-phase block 5V and the W-phase block 5W are each provided with a short circuit prevention time setting timer similar to the short circuit prevention time setting timer 5m). The short-circuit prevention time setting timer 5m operates as a one-shot timer.

One-shot timers 5bU, 5b are used as start triggers.
Either the rising or falling edge of the V, 5bW one-shot pulse, or only the falling edge can be selected. This selection is performed by the bit b6 of the waveform output mode register as shown in FIG. 6 described above. If this bit b6 is "0", it is "1" at both the rising and falling edges. For example, only the falling edge becomes the start trigger.

The short-circuit prevention time setting timer 5m is, as shown in FIG. 8, a bit of the pulse output data register 0.
The count source is set by b6 and b7. Bits b6, b7
If is "00", f ₂ (source oscillation divided by 2 clock)
Is "01", f ₄ (source oscillation divided by 4 clock)
But if "10" f _{8 (8-divided} clock of the source oscillation) is selected respectively.

When a value is written to the short circuit prevention time setting timer 5m, the short circuit prevention time setting timer for each phase block 5U (5V, 5W)
The value is written in the reload register 5l shared by 5m and the like. Short-circuit prevention time setting timer 5m etc. is for each block 5U, 5V, 5W one-shot timer 5bU (5bV, 5bW)
When a start trigger is given from, the value held in the reload register 5l is loaded into the built-in counter, and down counting is performed by the count source set in the timer mode register.

Further, each short-circuit prevention time setting timer 5m or the like can accept a trigger again before the operation by the previous trigger is completed. In this case, the trigger transfers the contents of the reload register 5l to the short-circuit prevention time setting timer 5m, and then the value is down-counted. The short-circuit prevention time setting timer 5m operates as a one-shot pulse timer. Therefore, when a trigger is given, it starts pulse output and down count, and when the content becomes "00H", it stops pulse output and stops operation. Wait until the trigger is given.

The output polarity of the three-phase waveform is determined by the output polarity setting toggle flip-flop 5k. When the content of the output polarity setting toggle flip-flop 5k is "0", the positive phase waveform of the three-phase waveform outputs "H" level, and when it is "1", the "L" level is output (three-phase) The waveform output is output in negative logic). The output polarity setting toggle flip-flop 5k has output polarity setting buffers corresponding to the U phase, V phase and W phase shown in FIG. 8, respectively, and the content of the counter of the cycle setting timer 5a becomes "0000H". At that time, the contents of the output polarity setting buffer are set in the output polarity setting toggle flip-flop 5k.

The automatic mode is set by setting the content of the bit b4 (automatic three-phase mode selection bit) of the waveform output mode register shown in FIG. 6 to "1". In this case, the output polarity setting buffers corresponding to the U phase, V phase, and W phase shown in FIG. 8 are invalidated, and the pulse output data registers 1 and 0 have the bit configurations shown in FIG. become.

When the automatic mode is set, the automatic output polarity setting of bit b3 of the waveform output mode register shown in FIG. 6 is set when the content of the counter of the cycle setting timer 5a becomes "0000H". The contents of the flip-flop 5g are inverted, and the inverted automatic output polarity setting flip-flop 5g
Is set in the output polarity setting toggle flip-flop 5k corresponding to each U-phase, V-phase and W-phase. After that, the contents of the output polarity setting toggle flip-flop 5k is the timer (one shot timer) corresponding to the blocks 5U, 5V, 5W of each phase.
Each time the one-shot pulse of (5bU, 5bV, 5bW) ends, its polarity is inverted.

Next, the waveform output operation will be described with reference to the waveform diagram of FIG. 10 showing an example of the U-phase waveform output in the automatic mode.

In the automatic mode, FIG. 10 (c) and FIG. 10 (d)
As shown in, when data is set in the reload register 1 5c and reload register 2 5d of the one-shot timer 5bU at the same time, when the content of the one-shot timer 5bU becomes "0000H", each one is selected by the selector 5s. Data can be alternately transferred from the reload registers 1 5c and 2 5d to the one-shot timer 5bU.

Set to bit b5 of the waveform output mode register
Writing "1" and operating the one-shot timer 5bU activates the three-phase waveform output mode. Fig. 10 (a) and Fig. 10
As shown in (b), when the content of the one-shot timer 5bU counter reaches “0000H”, the content of the one-shot timer 5bU register is transferred to the one-shot timer 5bU and starts one-shot pulse output. At this point, as shown in FIGS. 10 (e) and 10 (f), the contents of the automatic output polarity setting flip-flop 5g (in this case, "0") are set in the output polarity setting toggle flip-flop 5k. It

When the one-shot pulse output from the one-shot timer 5bU is completed, the contents of the output polarity setting toggle flip-flop 5k are changed to "" as shown in FIG. 10 (f).
At the same time as inverting from “0” to “1”, as shown in FIG. 10 (g), the time when the “L” level of the U-phase waveform and its opposite phase, the # U-phase waveform, does not overlap is set. 8-bit short-circuit prevention time setting timer (dead time timer) One-shot pulse of 5 m is output.

In this case, as shown in FIG. 10 (h), the output of the U-phase waveform started from the "H" level is output by the one-shot pulse output of the one-shot timer 5bU to the output polarity setting toggle flip-flop 5k. Even if the content is inverted from "0" to "1", "H" level is output until the short-circuit prevention time setting timer 5m outputs the one-shot pulse.

When the one-shot pulse of the short-circuit prevention time setting timer 5m ends, the already inverted output "1" of the output polarity setting toggle flip-flop 5k becomes valid, and the U-phase waveform shifts to "L" level. After that, when the content of the counter of the one-shot timer 5bU becomes "0000H", the content of the reload register 25d of the one-shot timer 5bU is transferred to the one-shot timer 5bU and the one-shot pulse output is started. At the same time, the contents of the automatic output polarity setting flip-flop 5g are inverted (in this case "1"), the inverted contents are set in the output polarity setting toggle flip-flop 5k, and the U-phase waveform output remains at the "L" level. Becomes

When the one-shot pulse output of the one-shot timer 5bU ends, the content of the output polarity setting toggle flip-flop 5k is inverted from "1" to "0", and at the same time, the one-shot pulse output of the short-circuit prevention time setting timer 5m is changed. Be started. When the content of the output polarity setting toggle flip-flop 5k changes from "1" to "0", the output of the U-phase waveform has an output level of "L" without waiting for the end of the one-shot pulse output of the short-circuit prevention time setting timer 5m. "From"
Change to H ".

In the automatic mode, by setting bit b4 (interrupt interval control bit of one-shot timer 5bU) of the pulse output data register to "0",
One shot timer, as indicated by INT on 10
By setting the interrupt interval of 5bU every other time and setting it to "1", the interrupt generation interval can be set every two times.

Also, the bits of the pulse output data register
By setting b5 (one-shot timer 5bU interrupt valid output polarity setting bit) to "0", the one-shot timer 5bU interrupt is output when the U-phase output polarity setting toggle flip-flop 5k is at "L" level. It can be generated, and by setting it to "1", the interrupt of the one-shot timer 5bU can be generated when the content of the U-phase output polarity setting toggle flip-flop 5k is at "H" level.

In the automatic mode, it is impossible to generate an interrupt for each interrupt of the one-shot timer 5bU.

By repeating the above operation, a U-phase waveform is generated as shown in FIG. 10 (h). As shown in Fig. 10 (i), the #U phase waveform, which is the opposite phase of this U phase waveform, is a signal whose content is reversed in the output polarity setting toggle flip-flop 5k when it is the U phase waveform. The contents of the operation are similar to those in the case of generating the U-phase waveform. In this way, the U-phase waveform output and the opposite phase #U
A waveform whose "L" level does not overlap with the phase waveform is output from terminals P5 ₅ and P5 ₄ . The width of the "L" level can also be made variable by changing and setting the value of the one-shot timer 5bU and the value of the period setting timer 5a.

V phase, W phase and their opposite phases, #V phase,
Also for #W phase, one-shot timer 5b corresponding to them
Similar operations are performed at V and 5bW to generate waveforms.

Although the above description is an example of generating a three-phase waveform by triangular wave modulation (also called double-edge modulation), three-phase waveform generation by sawtooth wave modulation (also called single-edge modulation) is also possible for each phase. This can be achieved by fixing the starting level of.

The bit of the pulse output data register
If b5, bit b6, bit b7 (“H” output polarity setting buffer for U, V, W phases) are set to “1”, U phase, V phase,
Each output level of W phase is controlled by timer, output polarity setting buffer,
It can be fixed at "H" regardless of the automatic mode type. Three-phase waveform generated in this way (U phase, V
Phase, W phase) and its opposite phase waveform (#U phase, #V phase, #W phase) are the waveform output control bit (bit b) of the waveform output mode register.
It is output from each port by setting 7) to "1". When this bit is set to "0", each port is in a floating state. In addition, this bit is commanded
In addition to setting to "0", even if a falling edge is input to the external interrupt #INT ₀ input terminal or a reset signal is input to the Rset input terminal to reset, "0"
You can

Next, description will be given of a case where an example of conventional U-phase waveform output is performed by the microcomputer with a built-in motor control circuit of the present invention.

Set to bit b1 of the U phase output polarity setting buffer
Writing "0" and operating the one-shot timer 5bU activates the three-phase waveform output mode.
When the content of the 5bU counter reaches "0000H", the content of the reload register 1 5c of the one-shot timer 5bU is transferred to the one-shot timer 5bU and the one-shot timer 5bU
Starts one-shot pulse output. At this point, the contents of the U-phase output polarity setting buffer (“0” in this case) are set in the output polarity setting toggle flip-flop 5k.

When the one-shot pulse output from the one-shot timer 5bU ends, the contents of the output polarity setting toggle flip-flop 5k are inverted from "0" to "1", and at the same time,
The one-shot pulse of the 8-bit short-circuit prevention time setting timer 5m that sets the time when the "L" level of the U-phase waveform and its opposite phase, the # U-phase waveform, does not overlap is output. "H"
The output of the U-phase waveform starting from the level is controlled by the one-shot timer 5bU's one-shot pulse output, even if the content of the output polarity setting toggle flip-flop 5k is inverted from "0" to "1". Until the one-shot pulse output ends, "H" level is output.

When the one-shot pulse of the short-circuit prevention time setting timer 5m ends, the already inverted output "1" of the output polarity setting toggle flip-flop 5k becomes valid, and the U-phase waveform changes to "L" level. Next, "1" is written in the bit b1 of the U-phase output polarity setting buffer before the content of the counter of the one-shot timer 5bU becomes "0000H" again. After that, when the content of the counter of the one-shot timer 5bU becomes "0000H", the content of the reload register 1 of the one-shot timer 5bU is transferred to the one-shot timer 5bU, and the one-shot timer 5bU one-shot pulse output is started. At the same time, "1" written in the U-phase polarity setting buffer is the output polarity setting toggle flip-flop.
It is set to 5k and the U-phase waveform output remains at the "L" level.

When the one-shot pulse output of the one-shot timer 5bU is completed, the content of the output polarity setting toggle flip-flop 5k is inverted from "1" to "0", and at the same time, the one-shot pulse output of the short-circuit prevention time setting timer 5m is changed. Be started. When the content of the output polarity setting toggle flip-flop 5k changes from "1" to "0", the output of the U-phase waveform has an output level of "L" without waiting for the end of the one-shot pulse output of the short-circuit prevention time setting timer 5m. "From"
Change to H ".

FIG. 16 is a block diagram showing a specific layout of the motor control circuit-embedded microcomputer of the present invention.

In FIG. 16, reference numeral 15a is a CPU (central processing unit), 15b is a RAM, 15c is a ROM, 15d is an oscillator, 15e is a general-purpose port, and 15f is a timer unit.
Reference numeral 15g indicates an AD converter, 15h indicates a DMAC (direct memory access controller), 15i indicates a bus interface unit, and 15j indicates other peripheral circuits. These are molded on the same chip and constitute a one-chip microcomputer.

In the above-described embodiment, each data (timer data, start level setting data, etc.) is set by the interruption of the CPU, but here, the motor of the present invention is added by adding DMAC to the above-mentioned embodiment. It constitutes a microcomputer with a built-in control circuit.

Each data (timer data, start level setting data, etc.) is generated by the CPU interrupt as in the conventional example.
When setting the above, it is inevitable that the shorter the cycle of the cycle setting timer 5a, the larger the load on the CPU for each data setting. In order to avoid such a situation,
Uses DMAC for each data setting. Trigger signal of cycle setting timer 5a or one-shot timer 5b for U phase, V phase, W phase.
It is configured to transfer to a timer register from a register or a certain memory address by a trigger signal of U, 5bV, 5bW.

FIG. 13 is a block diagram showing a configuration example of an AD converter of the microcomputer with a built-in motor control circuit of the present invention.

In FIG. 13, reference numeral 13a is a selector, 13b is an AD mode register, 13c is a comparator, 13d is a resistor ladder, 13e is an AD conversion data buffer, and 13f is a decoder.

In the present embodiment, the selector 13a has AN0 to AN7.
Up to 8 input terminals are provided. This selector 13a
The analog signals input to the input terminals AN0 to AN7 of
The decoder 13f selects at the sampling cycle set in the AD mode register 13b. AD conversion is performed by comparing the selected analog signal with the voltage value generated by the resistance ladder 13d by the comparator 13c.

By the way, the AD used in the motor control circuit built-in microcomputer of the present invention.
In the converter, the selector 13a and the decoder 13f are improved so that the sampling cycle for the analog input information can be divided into two types according to the required frequency.

The operation of the AD converter will be described below with reference to the schematic diagram showing the transition state of the sampling period.

The decoder 13f selects the analog input terminals AN0 to AN7 at two kinds of sampling periods set by the AD mode register 13b, but as shown in FIGS. Mode register 13
By setting the sweep terminal setting bit of b, the order of the input terminals to be selected can be set arbitrarily.

For example, it is assumed that the analog input terminals AN0 and AN1 are used frequently and the analog input terminals AN2 to AN4 are used less frequently. These analog input pins AN0 to
When the input signal to AN4 is AD converted, if the sweep pin setting bits (b8 to b10) are set to "101", as shown in Fig. 12, three inputs are sampled in one cycle and each of them is sampled. The analog input terminals AN0 to AN4 are sampled in such a sequence that the input terminals AN0 and AN1 are always sampled in one cycle, and the input terminals AN2, AN3 and AN4 are sampled once in each cycle. AD conversion is performed.

[0087]

As described above, according to the present invention, since the start level of the three-phase PWM waveform is automatically inverted by hardware, the conventional setting by CPU interrupt processing is unnecessary. .. Therefore, the program load is reduced. Also, by configuring the CPU interrupt to be set every few times, the interrupt is generated only when the software service needs to be performed, so that the time spent in the CPU interrupt processing can be reduced.

Conventionally, since the reload register of the timer was composed of one stage, it was necessary to set the next cycle data of the three-phase PWM each time by the CPU interrupt processing generated every three-phase PWM cycle. However, in the present invention, the reload register is configured in two stages and the setting data is alternately transferred from each reload register to the timer, so that the number of times of setting the timer data is reduced.

Further, each data (timer data, timer data, etc.) such as data read from the data table in the interrupt processing of the CPU or data calculated by calculation as in the prior art is used.
When setting the start level setting data, etc.), the shorter the cycle of the cycle setting timer, the larger the CPU load for each data setting. However, in the present invention, by using the DMAC, the time spent for data setting in the interrupt processing of the CPU can be reduced, so that the load on the CPU can be made zero.

Further, since the sampling period of the AD converter can be set to two types, AD conversion processing corresponding to the required frequency of analog input information becomes possible.

As described above, according to the present invention, the load of CPU execution processing can be reduced and real-time control and processing can be realized. In the conventional technology, when the control of the three-phase PWM waveform output, which is the object of the present invention, is performed, the higher the frequency of the three-phase PWM, the higher the CPU load for setting the three-phase PWM data becomes. It was impossible to control the high-frequency three-phase PWM. In addition, in AD conversion, the sampling period for analog input information could not be divided into the required frequency, and the sampling time for AD conversion was generally long, so if you want to use the AD conversion value for PWM output data, However, the present invention solves these problems.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a microcomputer as a conventional example.

FIG. 2 is a block diagram showing the configuration of a timer unit in FIG.

FIG. 3 is a block diagram showing a configuration of an 8-bit reload timer shown in FIG.

FIG. 4 shows the dead time timer shown in FIG. 3 and FIG.
It is a block diagram which combined with the timer unit shown by FIG.

FIG. 5 is a block diagram showing a configuration of a three-phase waveform generating circuit which is a main part of the motor control circuit-embedded microcomputer of the present invention.

FIG. 6 is a schematic diagram showing a bit configuration of a waveform output mode register.

FIG. 7 is a schematic diagram showing a configuration of a timer mode register.

FIG. 8 is a schematic diagram showing a configuration of a pulse output data register and contents in a three-phase mode.

FIG. 9 is a schematic diagram showing a configuration of a pulse output data register and contents in an automatic three-phase mode.

FIG. 10 shows U as an example of a three-phase waveform output in the automatic mode.
It is a waveform diagram which shows a phase waveform output.

FIG. 11 is a schematic diagram showing a transition of a sampling period of a conventional AD converter.

FIG. 12 is a schematic diagram showing the transition of the sampling cycle of the AD converter of the microcomputer with built-in motor control circuit of the present invention.

FIG. 13 is a block diagram showing a configuration of an AD converter of a microcomputer with a motor control circuit according to the present invention.

FIG. 14 is a schematic diagram showing a configuration of an AD mode register and a setting state of sweep terminal setting bits.

FIG. 15 is a schematic diagram showing a configuration of an AD mode register and a setting state of sweep terminal setting bits.

FIG. 16 is a block diagram showing a specific layout of the microcomputer with a built-in motor control circuit of the present invention.

FIG. 17 is a schematic diagram showing a configuration when a conventional three-phase inverter motor is controlled using a microcomputer.

FIG. 18 is a schematic diagram showing an actual configuration when a conventional three-phase inverter motor is controlled using a microcomputer.

FIG. 19 is a block diagram showing a configuration of the invention disclosed in Japanese Patent Laid-Open No. 3-70475 as a conventional principle.

[Explanation of symbols]

 15a Central processing unit (CPU) 15d Clock generation circuit 15e I / O port 5a Cycle setting timer 5b U U-phase one-shot timer 5bV V-phase one-shot timer 5b W W-phase one-shot timer 5g Automatic output polarity setting flip-flop 5f Flip-flop for setting interrupt interval 5c U-phase one-shot timer reload register 1 5d U-phase one-shot timer reload register 2 15h DMAC (Direct Memory Access Controller)

Claims (2)

[Claims] 1. A three-phase inverter motor comprising a central processing unit and a clock generating means for generating a clock, converting a pulse width modulation output generated in accordance with an analog signal given from the outside into an inverter output waveform. In a microcomputer with a built-in motor control circuit for generating a three-phase signal for control, three three-phase inverter waveform generation timers for generating output pulses based on a rising pulse synchronized with the clock, and these three-phase inverter waveform generations A pulse width modulation output generation circuit having a start level setting circuit for automatically inverting the start level of the timer each time one cycle elapses or setting it according to a preset pattern, and the three-phase inverter waveform generation timer It has two registers for setting the clock value of A timer data setting circuit for alternately setting the set value of the resistor in the three-phase inverter waveform generation timer, and an interrupt processing timing for setting values in the two registers of the timer data setting circuit from the central processing unit Is a digital signal obtained by sampling an interrupt processing circuit that is generated when the three-phase inverter waveform generation timer counts a plurality of times and a plurality of externally applied analog signals at different preset frequencies. A microcomputer with a built-in motor control circuit, which is equipped with an AD converter for converting and inputting into the. 2. The direct memory access controller is provided, and the data to be set in the three-phase inverter waveform generation timer is transferred to the two registers by direct memory access transfer. Microcomputer with built-in motor control circuit.