JPH04225409A - Microcomputer system - Google Patents

Abstract

PURPOSE:To reduce the burden of a CPU by providing a means which holds the data in addition to a conventional timer and a means which processes the held data after a prescribed time. CONSTITUTION:The processing means include a 2nd counter 15 which counts down its value at each prescribed time passed, a shift circuit 17 which rotates at each prescribed time, an adder/subtractor circuit 19 which adds or subtracts the contents of a comparison register 120 at each prescribed time, etc. Therefore a part or the whole of the processing to be carried out by a CPU can be carried out by the hardware of a timer with a signal (a) received from the timer when a prescribed time passed. As a result, the burden of the CPU is reduced and the overall processing time of a single chip microcomputer can be shortened.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a data processing device.
For example, it relates to a technique that is effective for use in a timer built into a single-chip microcomputer.

0002

2. Description of the Related Art A timer built into a single-chip microcomputer is composed of, for example, a counter, a comparison register, a comparator, etc., and the counter is counted up according to a designated clock. The contents of the counter and the comparison register are constantly compared by a comparator. When the above counter overflows or the contents of the above counter and the above comparator match, the CPU
(central processing unit
: can request an interrupt to the central processing unit. The CPU performs predetermined processing in response to this interrupt request.

However, when the CPU performs the above processing, it must interrupt other processing, resulting in a reduction in the execution time of the entire processing to be executed by the single-chip microcomputer. Furthermore, software must be developed to implement the above processing, which increases the development period for a system using the single-chip microcomputer.

On the other hand, there are examples of timers that change the output level of a predetermined output terminal when the predetermined time is reached, and examples of timers that are equipped with multiple sets of comparison registers and comparators. ) Published by Hitachi, Ltd. in December 1988.
H8/532HD6475328 HD643532
8 Hardware Manual, etc. these are,
Although it is possible to output square waves and the like without the intervention of software, anything other than simple waveform output must be executed by software.

[0005]

SUMMARY OF THE INVENTION The present inventor has studied a system controlled using the timer of the single-chip microcomputer described above. For example, to control a four-pole, two-phase stepping motor, at least four output terminals are required to control both ends of two coils that drive the stepping motor, as shown in FIG. For these terminals, general-purpose output ports or input/output ports of a single-chip microcomputer may be used. However, it is necessary to prevent both ends of these coils from going high at the same time. In this case, the CPU
The output data must be changed every time the stepping motor rotates one step, and the number of rotations of the stepping motor must be managed. In this way, in control using a single-chip microcomputer timer, depending on the application, C
The burden on PU becomes extremely large.

An object of the present invention is to minimize the increase in hardware in a system using a timer while
The object of the present invention is to provide a timer that minimizes PU intervention.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0008]

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows.

In other words, in addition to the conventional timer which includes means for counting, that is, a counter, a comparison register for holding a predetermined count value, and a comparator for comparing the contents of the counter and the contents of the comparison register, The data holding means is provided with a holding means and a means for processing the data held in the data holding means after a predetermined period of time has elapsed. For example, the means for processing the data includes a second counter that counts down every time the predetermined time elapses, a shift circuit that rotates the data every time the predetermined time elapses, and a second counter that counts down every time the predetermined time elapses. An addition/subtraction circuit or the like is provided that adds or subtracts the contents of the comparison register at each elapsed time. The means for processing the data may have a data holding function.

0010

[Operation] According to the above-mentioned means, after a predetermined period of time has elapsed,
Depending on the signal from the timer, some or all of the processing that should be performed by the CPU can be performed by the timer hardware, reducing the burden on the CPU and improving the overall processing time of single-chip microcomputers. can do.

[0011]

[Example] Figure 23 shows a single-chip microcomputer.
FIG. Although the single-chip microcomputer 8 is not particularly limited, the timer 1, C
PU2, ROM for program retention (read onl
y memory: read-only memory) 3, RAM for data retention (random access memory)
ry: occasional recall memory) 4, SCI (seria
l communication interface
: Serial communication interface) 5
Functional blocks such as input/output port 6 and input/output port 6 are formed on one semiconductor substrate. The above blocks are interconnected by an internal bus 7. The internal bus 7 is, for example,
It consists of a data bus, address bus, read/write signals, system clock, interrupt signals, etc. There is a path 9 that connects the timer 1 directly to the input/output port 6b without going through the internal bus 7. CPU2
sequentially reads out instructions or data stored in the ROM 3, operates the timer 1, the SCI 5, and the input/output port 6, and executes predetermined processing.

An embodiment in which the timer of the present invention is applied to the control of a stepping motor will be shown below.

[Embodiment 1] FIG. 1 is a block diagram showing a first embodiment of a timer according to the present invention. Although not particularly limited, the timer in FIG. 1 is a 16-bit counter 1.
1, 16-bit comparison register 12, 16-bit comparator 13, timer control status register 14
1, a second counter 15, a control logic block 101, a bus interface 110, etc. The counter 11 is counted up according to a designated clock. The contents of counter 11 and comparison register 12 are constantly compared by comparator 13. Second counter 15
is a 16-bit counter, although it is not particularly limited, and the input clock of the second counter 15 is a compare match signal that indicates that the contents of the counter 11 and the comparison register 12 match, and each time a compare match occurs, The second counter 15 is counted down. Counter 11, comparison register 12, timer control status
Although not particularly limited, the task register 141 and the second counter 15 are addressed to the memory space of the CPU 2, and the data register TM in the timer module
The CPU 2 can read/write data via the DB, bus interface 110, and internal data bus.

FIG. 2 shows the bit configuration of the timer control status register 141 in the first embodiment. Bits 1 and 0 are clock selection bits 1 and 0 (CS
K1, CSK0), which is an internal clock 3 which is the frequency-divided system clock of a single-chip microcomputer.
Select whether to use the type or external clock as the input clock for the counter 11. Bit 2 is a counter clear bit (CCLR), which clears the counter 11 when the contents of the counter 11 and comparison register 12 match.
Select whether to clear or not. Bit 3 is a counter enable bit (CNTE), which selects whether the counter 11 performs a count-up operation or stops. bit 13
is a zero detection flag (ZF), and when the contents of the second counter 15 match H'0000, the zero detection flag (ZF) is set to "1"(H' represents a hexadecimal number). Bit 14 is an overflow flag (OVF), and the content of counter 11 is H'FFFF⇒H'0000.
Then, the overflow flag (OVF) is set to "1". Bit 15 is the compare match flag (CM
F), and when the contents of the counter 11 and the comparison register 12 match, the compare match flag (CMF) is set to "1".
is set to When these flags are set to "1", an interrupt is requested to the CPU 2.

When controlling a stepping motor,
Based on the software on the ROM 3, the CPU 2 sets a value corresponding to the operating speed of the stepping motor in the comparison register 12, and sets a value corresponding to the number of steps in which the stepping motor rotates in the second counter 15. Also,
The clock selection bits 1 and 0 (CSK1, CSK0) of the timer control status register 141 are set to a value corresponding to the operating speed of the stepping motor, and the counter clear bit (CCLR) is set to "1". Although not particularly limited, it is assumed that the clock selection bits 1 and 0 (CSK1, CSK0) select a signal obtained by dividing the system clock by two. Thereafter, the counter enable bit (CNTE) is set to "1" to start the timer operation. The counter 11 starts counting from H'0000, and counts up by one at each falling edge of the signal obtained by dividing the frequency of the system clock by two, although this is not particularly limited. When the contents of the counter 11 and the comparison register 12 match, the contents of the second counter 15 are counted down, the compare match flag (CMF) of the timer control status register 141 is set to "1", and the CPU 2 request an interrupt. When the CPU 2 receives an interrupt, it rotates the data being output to the port once, and outputs this data to the port. This causes the stepping motor to advance one step.

When a compare match between the counter 11 and the comparison register 12 occurs the number of times set in the second counter 15, the second counter 15 becomes H'0000 and a zero detection flag (ZF) is set in addition to the compare match flag (CMF).
) is set to "1" and requests an interrupt to the CPU2. As a result, the stepping motor has rotated in a predetermined step, so when the CPU 2 receives the zero detection interrupt, it clears the counter permission bit (CNTE) to "0" and stops the timer operation, although there are no particular restrictions. let Although there is no particular restriction, at this time, the counter 11 is H'0000 and the second counter 15 is H'FF.
Stops in FF state. After that, the CPU 2 instructs the next operation.

Although there is no particular restriction, each time a compare match interrupt occurs, the CPU 2 executes an instruction to
By decreasing the value of the comparison register 12, the frequency of compare matches increases, the speed of the stepping motor can be gradually increased, the torque of the motor can be reduced, and the device can operate smoothly. can.

In this first embodiment, there is no need for the CPU 2 to manage the rotational speed of the stepping motor;
The load on the PU can be reduced.

Furthermore, in the first embodiment, the second counter 15 may be composed of a counter and a comparator. Although the scale of the hardware is greater than a counter with a zero detection circuit, flexibility may be increased if the timer is used for purposes other than controlling a stepping motor.

[Embodiment 2] FIG. 3 is a block diagram showing a second embodiment of a timer according to the present invention. Although not particularly limited, the timer in FIG.
7. Control logic block 102 and bus interface 1
It is composed of 10 mag. The main difference between this embodiment and the first embodiment shown in FIG. 1 is that a data register 16 and a shift circuit 17 are added in place of the second counter 15. Although not particularly limited, the data register 16 is an 8-bit register as shown in FIG.
, 2, and 3, respectively, and it is possible to control both ends of the two coils. The shift circuit 17 is rotated to the left or right every time a compare match occurs. The data register 16 is connected to the CPU as in the first embodiment.
The CPU 2 reads/writes the data via the timer module internal data register TMDB, the bus interface 110, and the internal data bus.
It is considered writable.

FIG. 5 shows the bit configuration of the timer control status register 142 in the second embodiment. Clock selection bits 1 and 0 of bits 1 and 0 (CS
K1, CSK0), bit 2 counter clear bit (
CCLR), bit 3 counter enable bit (CNTE
), the overflow flag (OVF) of bit 14, and the compare match flag (CMF) of bit 15 are the same as in the first embodiment. However, instead of the zero detection flag (ZF) in bit 13, a shift direction selection bit (SHD) is added in bit 4 to select the shift direction of the shift circuit 17.

Similar to the first embodiment, the stepping mode
When controlling the motor, the CPU 2 sets a value corresponding to the operating speed of the stepping motor in the comparison register 12 based on the software on the ROM 3, and sets a value corresponding to the number of steps in which the stepping motor rotates in the RAM 3. Set to . Also, clock selection bits 1 and 0 (CSK1, CS
A value corresponding to the operating speed of the stepping motor is set in K0), "1" is set in the counter clear bit (CCLR), and "0" is set in the shift direction selection bit (SHD). It is assumed that a leftward shift is selected by the shift direction selection bit (SHD), although there is no particular restriction. Thereafter, the counter enable bit (CNTE) is set to "1" to start the timer operation. Counter 11 is H'0
Counting is started from 000, and the count is increased by 1 at the falling edge of the signal obtained by dividing the frequency of the system clock by 2, although this is not particularly limited. When the contents of the counter 11 and the comparison register 12 match, the data register 16
The shift circuit 17 shifts the contents of 1 to the left once, sets the compare match flag (CMF) of the timer control status register 142 to "1", and requests an interrupt to the CPU 2. When the CPU 2 receives the interrupt, it updates the number of rotations of the stepping motor stored in the RAM 3. This causes the stepping motor to advance one step.

When the number of rotations of the stepping motor stored in the RAM 3 reaches a predetermined number of rotations, the CPU 2 clears the counter permission bit (CNTE) to "0", stops the timer operation, and starts the next operation. Instruct.

In this second embodiment, there is no need for the CPU 2 to control data rotation, etc.
can reduce the burden of

[Embodiment 3] FIG. 6 is a block diagram showing a third embodiment of a timer according to the present invention. Although not particularly limited, the timer in FIG. It is composed of a block 103, a bus interface 110, and the like. The third embodiment is a combination of the first and second embodiments.

FIG. 7 shows the bit configuration of the timer control status register 143 in the third embodiment. Clock selection bits 1 and 0 of bits 1 and 0 (CS
K1, CSK0), bit 2 counter clear bit (
CCLR), bit 3 counter enable bit (CNTE
), bit 4 shift direction selection bit (SHD), bit 13 zero detection flag (ZF), bit 14 overflow flag (OVF), and bit 15 compare match flag (CMF) according to the first implementation. This is similar to the example and the second embodiment.

Since this operation is similar to the first embodiment and the second embodiment, detailed explanation will be omitted.

In this third embodiment, the timer can rotate data, count the number of steps, etc. without the intervention of the CPU 2.

[Embodiment 4] FIG. 8 is a block diagram showing a fourth embodiment of a timer according to the present invention. Although not particularly limited, the timer in FIG. 8 includes a counter 11, a comparison register 120, a comparator 13, and a timer control status.
task register 144, constant register 18, adder/subtractor 19
, control logic block 104 and bus interface 11
It is composed of 0, etc. The main difference between this embodiment and the first embodiment shown in FIG. 1 is that a constant register 18 and an adder/subtractor 19 are added in place of the second counter 15. Although the constant register 18 is not particularly limited, the number of constant registers 18 is 16.
The adder/subtractor 19 is a bit register, and the adder/subtractor 19 is a 16-bit register.
It is a bit arithmetic unit. Every time a compare match occurs, the contents of the comparison register 12 and the contents of the constant register 18 are added or subtracted by an adder/subtractor 19, and the result can be stored in the comparison register 120. The constant register 18 is addressed to the memory space of the CPU 2 as in the first embodiment, and the CPU 2 is read via the timer module internal data register TMDB, the bus interface 110 and the internal data bus. - Can be read/written.

FIG. 9 shows the bit configuration of the timer control status register 144 in the fourth embodiment. Clock selection bits 1 and 0 of bits 1 and 0 (CS
K1, CSK0), bit 2 counter clear bit (
CCLR), bit 3 counter enable bit (CNTE
), the overflow flag (OVF) of bit 14, and the compare match flag (CMF) of bit 15 are the same as in the first embodiment. Furthermore, an addition/subtraction selection bit (A/S) is added to bit 5, and an addition/subtraction enable bit (ASE) is added to bit 6. Addition/subtraction selection bit (A/
S) selects whether the adder/subtractor 19 performs addition or subtraction, and the addition/subtraction permission bit (ASE) selects whether the adder/subtractor 19 performs addition or subtraction.

In this embodiment, when controlling the stepping motor and gradually increasing the rotational speed, the first
Similarly to the embodiment described above, the CPU 2 sets a value corresponding to the initial operating speed of the stepping motor in the comparison register 12 based on the software on the ROM 3, and sets a value corresponding to the number of steps in which the stepping motor rotates in the RAM 3. Further, a value corresponding to the amount of increase per step in the operating speed of the stepping motor is set in the constant register 18. Also, the clock selection bits 1 and 0 (CSK1, CSK
Set the value corresponding to the operating speed of the stepping motor to SK0), "1" to the counter clear bit (CCLR), "0" to the addition/subtraction selection bit (A/S), and "0" to the addition/subtraction enable bit (ASE). Set 1”. Thereafter, the counter enable bit (CNTE) is set to "1" to start the timer operation. The counter 11 starts counting from H'0000 and counts up one by one. When the contents of the counter 11 and the comparison register 12 match, the contents of the constant register 18 are subtracted from the contents of the comparison register 12, and the contents of the timer control status register 1 are subtracted from the contents of the comparison register 12.
The compare match flag (CMF) of 44 is set to "1" and an interrupt is requested to the CPU 2. When the CPU 2 receives the interrupt, it updates the number of rotations of the stepping motor stored in the RAM 3. This causes the stepping motor to advance one step.

When the number of rotations of the stepping motor stored in the RAM 3 reaches a predetermined number of rotations, the CPU 2 clears the counter permission bit (CNTE) to "0", stops the timer operation, and starts the next operation. Instruct.

In this fourth embodiment, there is no need for the CPU 2 to perform control such as increasing the rotational speed, and the burden on the CPU can be reduced.

[Embodiment 5] FIG. 10 is a block diagram showing a modification of the fifth embodiment of the timer according to the present invention. Figure 1
Although there are no particular restrictions on the timer 0, the timer
1, comparison register 120, comparator 13, timer control status register 145, second counter 15,
Data register 16, shift circuit 17, constant register 1
8, an adder/subtractor 19, a control logic block 105, a bus interface 110, etc. The main difference between this embodiment and the first embodiment shown in FIG. 1 is that a data register 16, a shift circuit 17, a constant register 18, and an adder/subtractor 19 are added. That is, this embodiment is a combination of the third embodiment and the fourth embodiment.

FIG. 11 shows the timer control of the fifth embodiment.
2 shows the bit configuration of the file status register 145. Clock selection bits 1 and 0 (C
KS1, CKS0), bit 2 counter clear bit (CCLR), bit 3 counter enable bit (CNT
E), bit direction selection bit (SHD) of bit 4, addition/subtraction selection bit (A/S) of bit 5, addition/subtraction enable bit (ASE) of bit 6, zero detection flag (ZF) of bit 13, bit 14 bit -Bufflow Flag (OVF)
and the compare match flag (CMF) of bit 15 are the same as in the third and fourth embodiments.

In this embodiment, when controlling the stepping motor and gradually increasing the rotational speed, the fourth
Similarly to the embodiment described above, the CPU 2 sets a value corresponding to the initial operating speed of the stepping motor in the comparison register 120 based on the software on the ROM 3, and sets a value corresponding to the number of steps in which the stepping motor rotates in the comparison register 120. 2 counter 15, and a value corresponding to the amount of increase per step in the operating speed of the stepping motor is set in constant register 18. Also, clock selection bits 1 and 0 (C
Set the value corresponding to the operating speed of the stepping motor in KS1, CKS0) and the counter clear bit (CCLR).
1”, and “0” to the shift direction selection bit (SHD).
Set the addition/subtraction selection bit (A/S) to "0" and the addition/subtraction permission bit (ASE) to "1". Thereafter, the counter enable bit (CNTE) is set to "1" to start the timer operation. The counter 11 starts counting from H'0000 and counts up one by one. When the contents of the counter 11 and the comparison register 12 match, the contents of the data register 16 are shifted once to the left by the shift circuit 17, and the second counter 15 is counted down.
The contents of the constant register 18 are subtracted from the contents of the comparison register 12, and the compare match flag (CMF) of the timer control status register 145 is set to "1".
" to request an interrupt from the CPU2. Since there is no processing that the CPU2 should do in response to this interrupt request, this interrupt can be ignored. For example, set the interrupt mask bit inside the CPU2 to "1". Interrupts may be disabled by setting this to "0", or by providing a compare match interrupt enable bit in the timer control status register 145 and setting this bit to "0". Regarding how to disable this interrupt, please refer to the above-mentioned "H8/532HD6475328 HD6435" published by Hitachi, Ltd. in December 1988.
328 Hardware Manual, etc., so a detailed explanation will be omitted.

In the fifth embodiment, there is no need for the CPU 2 to control changes in rotational speed, management of rotational speed, rotation of data, etc., and the burden on the CPU can be reduced.

[Embodiment 6] FIG. 12 is a block diagram showing a sixth embodiment of a timer according to the present invention. The timer in FIG. 12 has a comparison register 12, a timer control/status register 14, and a comparison register 12, a timer control/status register 14, and
5. The constant registers 18 are each made up of two registers, forming a so-called double buffer configuration.

In this embodiment, when controlling the stepping motor and gradually increasing the rotational speed, the fifth
Similarly to the embodiment described above, the CPU 2 sets a value corresponding to the initial operating speed of the stepping motor in the comparison register 121 based on the software on the ROM 3, and sets a value corresponding to the number of steps in which the stepping motor rotates in the comparison register 121. 2 counter 15, and a value corresponding to the amount of increase per step in the operating speed of the stepping motor is set in constant register 181. Also, the clock selection bits 1 and 0 of the timer control status register 1451 (
CKS1, CKS0), set the value corresponding to the operating speed of the stepping motor, set the counter clear bit (CCLR) to "1", set the shift direction selection bit (SHD) to "0", and add/subtract selection bit (A/S). Set "0" to "0" and set "1" to the addition/subtraction enable bit (ASE). After that, when the counter enable bit (CNTE) is set to "1", these data are transferred to the comparison register 122, constant register 182 and timer control status register 1.
452 and starts the operation of the timer. After that, CPU2 reads the data for the next operation of the timer.
The data is set in the comparison register 121, constant register 181, and timer control status register 1451. The counter 11 starts counting from H'0000, and
Count up step by step. When the contents of the counter 11 and the comparison register 122 match, the contents of the data register 16 are shifted once to the left by the shift circuit 17, the second counter 15 is counted down, and the contents of the comparison register 122 are shifted once to the left by the shift circuit 17.
The contents of the constant register 182 are subtracted from the contents of the timer control status register 145.
The compare match flag (CMF) of the CPU 2 is set to "1" and an interrupt is requested to the CPU 2. Since there is no process that the CPU 2 should perform in response to this interrupt request, this interrupt may be ignored.

When a compare match between the counter 11 and the comparison register 122 occurs the number of times stored in the second counter 15, the zero detection flag (ZF) is set to "1", and the comparison register 121, constant register 181 and timer control - Data in status register 1451 is transferred to comparison register 122, constant register 182 and timer control status register 1452, respectively. Similarly to the above, an interrupt is requested to the CPU 2. CPU
2 accepts the zero detection interrupt, and compares data for the next operation of the timer with a register 121, a constant register 181, and a timer control status register 1.
Set to 451. Although not particularly limited, the counter permission bit (CNTE) is cleared to "0" to stop the timer operation. At this time, the counter 11 is H'00
It will stop at 00.

In the sixth embodiment, the motor can be rotated while increasing the rotational speed, and then rotated at a constant speed. There is no need to immediately accept an interrupt request, and the load on the CPU can be greatly reduced.

[Embodiment 7] FIG. 13 is a block diagram showing a seventh embodiment of a timer according to the present invention. The timer in FIG. 13 differs from the third embodiment in FIG. 6 in that the timer control status register 14 is an 8-bit register, and the timer control status register 147 is
, a timer control register 148, and a timer mode register 149.
53, and in addition to four timer data output terminals, a timer output terminal is added. second counter 151,
Second comparison register 152, timer control status
task register 147, timer control register 14
8 and the timer mode register 149 are addressed to the memory space of the CPU 2 as in the first embodiment, and are connected to the CPU via the timer module internal data register TMDB, the bus interface 110, and the internal data bus.
2 can be read/written.

FIG. 14 shows the timer control of the seventh embodiment.
2 shows the bit configurations of a timer status register 147, a timer control register 148, and a timer mode register 149. Bits 3 to 0 of the timer control status register 147 are output select bits 3 to 0 (OS3 to OS0), which determine how the output level of the timer output terminal is changed by a compare match or a second compare match. choose whether to do so. Output select bits 3 and 2 (OS3, OS2) are the second
The output level based on the compare match is selected, and the output select 1 and 0 bits (OS1, OS0) select the output level based on the compare match. Output select 1 and 0 bits (OS1, OS0) are both “0”
Even if a compare match occurs when , the output level of the timer output pin does not change. When the output select 1 bit (OS1) is "0" and the output select 0 bit (OS0) is "1", when a compare match occurs, the output level of the timer output terminal is set to low level. Output select 1 bit (OS1) is “1” and output select 0 bit (OS0) is “0”
When a compare match occurs, the output level of the timer output terminal becomes high level. Even if a compare match occurs when the output select 1 and 0 bits (OS1, OS0) are both "1", the output level of the timer output terminal is inverted. The same applies to the output select 3 and 2 bits (OS3, OS2). Although not particularly limited, if a compare match and a second compare match occur simultaneously, the timer output level changes in the order of inverted output, high level output, and low level output. In addition, output select bits 3 to 0 (OS3
~OS0) are all "0", no timer output is performed and the terminal is used as an input/output port. Bit 4 is a second overflow flag (OVF2) and is set to "1" when the second counter 151 becomes H'FFFF⇒H'0000. Bit 5 is a second compare match flag (CMF2) and is set to "1" when a second compare match occurs. Bit 6 is an overflow flag (OVF), and bit 7 is a compare match flag (CMF), and since these are the same as above, detailed explanation will be omitted.

Second counter clock selection bits 1 and 0 (C
KS21, CKS20) and selects the input clock of the second counter 151. Second counter clock selection bits 1 and 0 (CKS21, CKS20) are both “0”
”, the second counter 151 is the 16-bit counter 11
Due to the overflow of the counter 11, when the second counter clock selection bit 1 (CKS21) is "0" and the second counter clock selection bit 0 (CKS20) is "1", the second counter 151 is , second counter clock selection bit 1 (CKS21) is “1” and second counter clock selection bit 0 (CKS21) is “1” and second counter clock selection bit 0 (CK
S20) is "0", the second counter 151 uses the same clock as the counter 11, and the second counter clock selection bits 1 and 0 (CKS21, CKS20) are both "1".
”, the external clock input from the timer clock input terminal counts up. Bits 3 and 2 are clock selection bits 3 and 2 (CKS1, CK
S0) and selects the input clock of the counter 11. When clock selection bits 3 and 2 (CKS1, CKS0) are both "0", the counter 11 uses a clock obtained by dividing the system clock by two using a frequency divider (not shown), and sets clock selection bit 3 (CKS1) to "0". Also, when clock selection bit 2 (CKS0) is "1", a clock obtained by dividing the system clock by 4 causes clock selection bit 3 (CKS1) to be "1" and clock selection bit 2 (CKS0) to be "0". When the clock selection bits 3 and 2 (CKS1, CKS0) are both "1", the external clock input from the timer clock input terminal is counted up using a clock obtained by dividing the system clock by eight. Bit 7~
4 is compare match interrupt enable (CMIE), overflow interrupt enable (OVIE), second compare match interrupt enable (CMI2E), second overflow interrupt enable (
OVI2E) bit, and the compare match flag (CMF), overflow flag (OVF), second compare match flag (CMF2), and second overflow flag (OVF2) are set to "1", respectively. When C
Select whether or not to request an interrupt to PU2.

Bit 0 of the timer mode register 149 is the second counter clear bit (CCLR2), and when a second compare match occurs with this bit set to "1", the counter 11 and the second counter 151 go high.
Cleared to '0000. When this bit is "0", the count operation is not affected even if a compare match occurs. Bit 1 is a counter clear bit (CCLR), and when a compare match occurs with this bit set to "1", only the counter 11 is cleared to H'0000. When this bit is "0", the count operation is not affected even if a compare match occurs. Bits 3 and 2 enable counting 1 and 0 bits (CNTE1 and 0)
and count permission 1, 0 bits (CNTE1, 0)
When both are "0", both the counter 11 and the second counter 151 are stopped. When the count permission 1 bit (CNTE1) is “0” and the count permission 0 bit (CNTE0) is “1”, the count operation of the counter 11 and the second counter 151 is performed when the second compare match flag (CMF2) is “0”. is performed, and when the second compare match flag (CMF2) is “1”, the counter 1 is
Both the first and second counters 151 are stopped. When the count permission 1 bit (CNTE1) is "1", the counter 11 and the second counter 151 perform counting operations regardless of the value of the count permission 0 bit (CNTE0). Bit 4 is a bit direction selection bit (SHD), and when a compare match occurs, the data register 16
Select whether to rotate the contents to the left or right. Bit 5 is the timer data output enable bit (TMOE) and is the data register 16 bit.
Select whether or not to output the contents to the timer data output terminal.

FIG. 15 shows an example of operation timing when the timer of this embodiment is used to control a stepping motor. First, the contents corresponding to the rotational speed of the motor are stored in the comparison register 12.
Then, the contents corresponding to the rotational speed of the motor are set in the second comparison register 152. The second counter 151 inputs a second clock so that the input clock of the second counter 151 becomes the compare match signal of the counter 11.
Counter clock selection bits 1 and 0 (CKS21, CK
S20) are set to "0" and "1", respectively. The timer data output enable bit (TMOE) is set to "1" so that the contents of the data register 16 are output to the timer data output terminal. Set H'07 in the data register 16. count permission 1 so that the counter 11 and the second counter 151 are stopped by the second compare match;
0 bit (CNTE1, 0) as “0” and “1” respectively
, the counter clear bit (CCLR) is set to "1", the second counter clear bit (CCLR2) is set to "1", and the timer operation is started. Each time the counter 11 generates a compare match, the contents of the data register 16 are rotated to the left, and the motor rotates one step at a time. When the second compare match occurs, it means that the motor has rotated a predetermined number of revolutions, and the operation of the timer stops.

FIG. 16 shows the timer of this embodiment in PWM (P
An example of the operation timing used for output (ulse WidthModulation) is shown below. For example, the second counter clock selection bits 1 and 0 (CKS21
, CKS20) to "1" and "0", and clock selection bits 3 and 2 (CKS1, CKS0) to "0" and "0". The second compare match causes the counter 11 and the second
The second counter clear bit (CCLR2) is set to "1" so that the counter 151 is cleared to H'0000. Set the output select bits 3 to 0 (OS3 to OS0) to "0" so that a compare match results in a low level output, and a second compare match results in a high level output.
1", "1", "0". Then, count permission 1
Set the bit (CNTE1) to “1”. As a result, the waveform whose period is the second comparison register 152 and whose pulse width is the comparison register 12 can be output without the intervention of the CPU 2. In this usage example, the data register 16, shift circuit 17
Since it is not used, the hardware scale can be reduced by deleting it.

[Embodiment 8] FIG. 17 is a block diagram showing an eighth embodiment of a timer according to the present invention. The timer in FIG. 17 differs from the seventh embodiment in FIG.
1 can be divided into upper 8 bits and lower 8 bits, and the second comparator 153 is divided into upper 8 bits comparator 1532.
, a lower 8-bit comparator 1531. When the second counter 151 and the second comparator 153 are divided into upper 8 bits and lower 8 bits, it is possible to request an interrupt to the CPU 2 by a compare match of the lower 8 bits, and by a compare match of the lower 8 bits, the second
The lower 8 bits of the counter 151 are cleared to H'00, and the upper 8 bits are counted up.

In order to rotate the motor while reducing the torque of the motor, the contents of the comparison register 12 may be sequentially changed. The burden on the software can be further reduced by changing the contents of the comparison register 12 every predetermined number of compare matches. For example, using the above compare match of the lower 8 bits, write H to the lower half of the second comparison register.
If '4 is set, an interrupt can be accepted every four compare matches. If the contents of the comparison register 12 are changed every time the lower 8 bits are compared, the time interval at which the CPU 2 performs interrupt processing will be quadrupled.
During this time, the CPU 2 can perform other processing.

[Logic circuit example] FIG. 18 is a table showing special symbols used in logic circuit examples. FIG. 19 shows a specific logic circuit example of the counter circuit. FIG. 19 shows a typical 2-bit counter circuit. The counter circuit is connected to the timer module internal data bus TMDB and is always readable/writable, and can be cleared to all bits "0" by a counter clear signal. Although not particularly limited, carry is permitted by the counter clock generated by the falling edge of the clock selected by the clock selection bit. Series connected n-channel MOSFET (metal
oxide semiconductor field
When there is a carry from the lower bit through the effect transistor) circuit, the data of that bit is
The data is inverted by an ENOR (exclusive nor) circuit. Further, if that bit is also "1", a carry occurs to the higher order. If all bits are "1", an overflow signal will be generated the next time the counter clock is generated.

FIG. 20 shows a comparison circuit, FIG. 21 shows an addition/subtraction circuit,
FIG. 22 shows a specific logic circuit example of the shift circuit. Figure 2
0 to 22 typically each show a circuit for 2 bits.

According to the above embodiment, the following effects can be obtained. That is, by providing means for processing data other than the timer counter when a predetermined time has elapsed, the CPU 2 can change the rotational speed of the stepping motor, manage the number of rotations, and control the data. etc., and the load on the CPU can be reduced.

The invention made by the present inventors is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

For example, there are no limitations on the number or type of other functional blocks built into the single-chip microcomputer, or the configuration of the internal bus. Also,
The specific configuration of each block of the timer, such as the counter circuit and the comparison circuit, is not limited to the above embodiment, and can be modified in various other ways. Furthermore, it is also possible to configure the embodiments by combining them with each other, and it is also possible to take out and utilize a part of the embodiments.

[0055] In the above explanation, the invention made by the present inventor was mainly applied to a timer built in a single-chip microcomputer, which is the background field of application, but the present invention is not limited to this. However, the present invention is also applicable to other data processing devices, and the present invention can be applied to data processing devices having at least a timer and a processing device that controls the timer. For example, the CPU, ROM, RAM, timer, etc. do not need to be configured on a single semiconductor substrate, and can also be applied to multi-chip microcomputer systems.

[0056] This timer can also be applied to stepping mode.
It is not limited to motors, but can also be used to control various small motors such as brushless motors used in OA equipment, AV equipment, cameras, etc. by using it together with power drive elements such as power MOSFETs. can. Furthermore, various applications other than motor control are possible.

[0057]

Effects of the Invention The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, when a predetermined period of time has elapsed, by having the timer hardware perform part or all of the processing that should be performed by the CPU in response to a signal from the timer, the intervention of the CPU is reduced, and the timer is connected to the system bus. (
Since it can operate separately from the internal bus 7),
Meanwhile, the CPU can perform other processing, improving the overall processing time of the microcomputer.

Furthermore, since the amount of software can be reduced, the capacity of the ROM for storing programs built into the single-chip microcomputer can be reduced, and the chip size of the single-chip microcomputer can be reduced. This makes it possible to reduce the cost of single-chip microcomputers. on the other hand,
If the capacity of the ROM for storing programs built into a single-chip microcomputer is left as is, programs for other processing can be stored, expanding the range of system applications.

Furthermore, since the program becomes simpler and the amount of software can be reduced, the development period for a system using a single-chip microcomputer can be shortened, and the system can be controlled using a single-chip microcomputer. It is also possible to reduce the cost of the system.

[Brief explanation of the drawing]

[Figure 1] Block diagram of a timer in the first embodiment

[Figure 2] Bit configuration diagram of the timer control register of the first embodiment

[Figure 3] Block diagram of a timer in the second embodiment

[FIG. 4] Detailed block diagram of the data register 16 and shift circuit 17

[Fig. 5] Bit configuration diagram of the timer control register of the second embodiment

[Fig. 6] Block diagram of a timer in the third embodiment

[Fig. 7] Bit configuration diagram of the timer control register of the third embodiment

[Fig. 8] Block diagram of a timer of the fourth embodiment

[Fig. 9] Bit configuration diagram of the timer control register of the fourth embodiment

FIG. 10 is a block diagram of a timer according to the fifth embodiment.

[Figure 11
] Bit configuration diagram of the timer control register of the fifth embodiment

[Fig. 12] Block diagram of a timer in the sixth embodiment

[Figure 13
] Block diagram of the timer of the seventh embodiment

[Fig. 14] Bit configuration diagram of timer control register, etc. of the seventh embodiment

[Figure 15] Example diagram of operation timing used to control a stepping motor

[Figure 16] Example diagram of operation timing used for PWM output

[
FIG. 17: Block diagram of a timer in the eighth embodiment

[Figure 18]
Symbols used in logic circuit examples

[Figure 19] Logic circuit example of counter circuit

[Figure 20] Logic circuit example of comparison circuit

[Figure 21] Logic circuit example of addition/subtraction circuit

[Figure 22] Logic circuit example of shift circuit

[Figure 23] Block diagram of single-chip microcomputer

[Figure 24] Example of stepping motor drive circuit

[Explanation of symbols]

1...Timer, 2...CPU, 3...ROM, 4...RAM, 5
...SCI, 6...I/O port, 7...Internal bus, 8...Single chip microcomputer, 9...Timer output, 1
1...Counter, 12...Comparison register, 13...Comparator, 1
41-149...Control status register, 1
5... Second counter, 16... Data register, 17... Shift circuit, 18... Constant register, 19... Addition/subtraction circuit, 10
1 to 108...Control logic block, 110...Bus interface

Claims (14)

[Claims] Claim 1: A timer comprising a counting means and a means for determining whether a counted value has reached a predetermined value, the timer comprising a data holding means and a data processing means, wherein the counting means counts. It is characterized in that the data held in the data holding means can be processed by the data processing means when the count value reaches a predetermined value. timer. 2. The timer according to claim 1, wherein said data processing means is adapted to perform subtraction processing. 3. The timer according to claim 1, wherein said data processing means is adapted to perform addition processing. 4. The timer according to claim 1, wherein said data processing means is adapted to perform shift processing. 5. The timer according to claim 1, wherein the processed data is held in the data holding means. 6. The timer according to claim 1, wherein part or all of the data held in the data holding means is outputted to the outside. 7. The timer according to claim 1, further comprising means for determining that the data held in said data holding means has reached a predetermined value. 8. A counting means, a means for determining whether the counted value has reached a predetermined value, a data holding means, and a data processing means, wherein the counted value counted by the counting means is a predetermined value. a timer configured to enable the data held in the data holding means to be processed by the data processing means upon reaching the value, and further comprising a data processing means. A microcomputer system characterized in that the timer is operated under the control of the data processing means. 9. The count value counted by the counting means is calculated by the data.
9. The microcomputer system according to claim 8, wherein the microcomputer system is adapted to be readable by a data processing device. 10. A microcomputer system according to claim 8, wherein said data processing device is capable of writing data held by said data holding means. 11. The microcomputer system according to claim 8, further comprising means for determining whether the data held in said data holding means has reached a predetermined value. 12. The data processing apparatus according to claim 8, further comprising means for transmitting to the data processing device that the data held in the data holding means has reached a predetermined value. microcomputer system. 13. A single-chip microcomputer, characterized in that the microcomputer system according to claim 8 is made up of a single semiconductor device. 14. A single-chip microcomputer system comprising the single-chip microcomputer according to claim 13 and a stepping mote.