JPH09237144A - Input and output controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to operate data with optional bit width without imposing load to a CPU by temporarily storing operation result information from a timer computing element in a count control circuit and outputting the stored information based upon an instruction from an instruction controller. SOLUTION: Timer data for I/O control are stored in a timer register(TR) and prescribed reference data for I/O control are stored in a comparator/capture register CR. The timer computing element (TE) executes operation based upon the timer data, the reference data and I/O data. The count control circuit to be a storage means consisting of an one-bit register and an AND circuit temporarily stores information OC such as the compared result and overflow of the element TE. When an overflow flag stored in the register is valid and an extension instruction EX from an instruction controller CTL is valid, their AND becomes true and outputs a count up enable signal EN to the element TE.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of an input / output control device, and more particularly, an input / output control device improved so that timer arithmetic processing included in the input / output control processing can be performed on data of an arbitrary bit width Regarding

[0002]

2. Description of the Related Art Since a timer arithmetic circuit included in an input / output control device is composed of a register for storing data, a comparator for comparing data, etc., the bit width of data that can be handled by arithmetic is usually Limited by these hardware. That is, for example, if the register or comparator is
In the case of 2 bits, the operation of data larger than 32 bits cannot be realized as it is. In this case, it is clear that if the necessary size of hardware is prepared, data operation with a larger bit width can be performed, but this is not only costly, but also physically increases the hardware. Therefore, it is not preferable from the viewpoint of integration. Therefore, in general, when an overflow occurs, that is, when the operation result exceeds the maximum value that can be handled by the prepared hardware, for example, C
A method of interrupting the PU and activating another program from the CPU to count the number of overflows has been used. Alternatively, when an overflow occurs, a signal is once output through the external terminal or the internal terminal and then re-input as the count-up enable signal, which means that the operation can be continued.
When this count-up enable signal is input,
A method has been used in which the processing for the overflow is executed according to the signal.

[0003]

However, the CPU
The method of interrupting the data not only puts a load on the CPU, but further, while the CPU is performing the processing requested by the interrupt, the input / output control device must prevent the next processing from being performed. There was also a problem that the consistency of could not be maintained. This is because the original purpose of the input / output control device is to perform C / I
This is obviously not preferable in view of reducing the load on the PU and increasing the processing speed.

In the method of outputting a signal indicating overflow through the terminal and re-inputting it as the count-up enable signal, the count-up enable signal is input / output in addition to the data to be originally controlled. The original efficiency of data input / output becomes poor. Also, when the count-up enable signal is input,
In order to execute the processing for the overflow according to the signal, it is necessary to register the processing as the processing executed according to the input / output data, but the number that can be registered as such processing. However, if the process for overflow is registered, the number of processes that can be registered for the original input / output control will be reduced accordingly. That is, this method also sacrifices the original function and performance of the input / output device, and is not preferable.

In view of the above-mentioned problems of the prior art, the present invention is an input / output capable of performing arithmetic operation on data of an arbitrary bit width without imposing a load on the CPU and satisfying the original function and performance. An object is to provide a control device.

[0006]

According to the present invention, in an input / output control device for controlling input / output of input / output data, first storage means for storing timer data relating to the input / output control, and the input / output control. Second storage means for storing the predetermined reference data according to the above, operation means for performing operation based on at least one of the timer data, the reference data and the input / output data, and operation result of the operation And a command control unit for sending a command related to the calculation to the first, second and third storage units and the calculation unit. When the predetermined arithmetic operation is performed, the third storage means sends the information stored in the third storage means to the arithmetic means based on an instruction from the instruction control means, Upon calculating means performs the calculation, and is characterized in that usable calculation results to such information of the operation performed on the predetermined operation earlier.

The timer data is data which is sequentially counted up or down according to the system clock, and the reference data is data which is preset to a predetermined value. The meaning or role of these data is defined in the input / output processing program and is not particularly limited. As an example, when performing a process of inverting the output at a predetermined interval, the predetermined interval is stored as reference data, the timer data is sequentially counted up from 0, and the comparison operation is performed with the reference data. If the output is inverted at the time of coincidence, the output can be inverted at a predetermined interval.

The first and second storage means are registers or the like having a bit width sufficient to store data such as 16 bits or 32 bits, and can store one or more data. On the other hand, the third storage means is like a register or a latch circuit that can temporarily store a small amount of information such as 1 bit or 2 bits. The information stored in the third storage means specifically includes information indicating that an overflow has occurred in the calculation, information indicating the result of the comparison calculation of the timer data and the reference data, and the like. The capacity of the storage means may be determined according to the amount of information.

By sending the information stored in the third storage means to the arithmetic means, when the arithmetic means performs the arithmetic operation, the information on the arithmetic result of the arithmetic operation performed before the predetermined arithmetic operation. Using, for example, when the first storage means can store only 16-bit data and the arithmetic means is also a 16-bit arithmetic unit, the 32-bit timer data is converted into upper 16 bits and lower 16 bits. If two bits of 16-bit data are handled and the lower 16-bit data is counted up and an overflow occurs, the information indicating the overflow is stored in the third storage means, and the next calculation is performed. If the information is stored, the upper 16 bits of data are counted up, and if the information is not stored, nothing is done, and 32 bits are set. Means that such performs calculation of the timer data.

As another example, there is also a case where a comparison operation of 32-bit data is performed by a 16-bit arithmetic unit. That is, the lower 16 bits are compared and the comparison result is the third
If the upper 16 bits are compared and coincident with each other, it is possible to know from this information whether or not the lower bits coincide with each other. Therefore, by associating the results of two comparison operations with each other, 32-bit data is stored. The comparison result of will be understood. By repeating the same processing in this way, it is possible to perform data operation with a larger arbitrary bit width.

[0011]

According to the input / output control device of the present invention, a small-capacity storage means for temporarily storing the operation result of data is provided, and the operation result stored therein is referred to in the subsequent operation to obtain a plurality of data. By associating the arithmetic operations, it is possible to perform arithmetic operations on data having an arbitrary bit width larger than the bit width that can be handled by the arithmetic unit while not imposing a load on the CPU and satisfying the original function and performance.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an input / output control device of the present invention will be described in detail with reference to the drawings. First, the configuration and operation of the conventional input / output control device shown in FIG. 4 will be described.

The input / output control device of FIG. 4 includes a timer register TR corresponding to the first storage means, and a timer register address decoder M for performing address conversion processing when accessing timer data stored in the timer register.
UXT, compare / capture register CR corresponding to the second storage means, compare / capture register address decoder MUXC, timer calculator TE, terminal input / output device IOC, and instruction control device CTL Is. The command control device CT
L is a program counter PC, an instruction address decoder MUXP, an instruction storage device MEM, an instruction code decoder D
It is composed of EC and.

The input / output controller of FIG. 4 starts its operation when the CPU activates the program counter PC,
The operation is terminated by the CPU stopping the program counter PC. The processing performed by the input / output control device is stored as a program in the instruction storage device MEM, and the program counter PC specifies the address of the instruction to be executed. The address output by the program counter PC is decoded by the instruction address decoder MUXP and sent to the instruction storage device MEM, and the instruction storage device MEM outputs the corresponding instruction code to the instruction code decoder DEC. The instruction code decoder DEC decodes the instruction code and sends the decoded instruction to the timer register CR, the compare / capture register CR, the timer arithmetic unit TE, the terminal input / output device IOC and the like.

The timer register TR is a command controller CT.
When the timer register address TA is received from L, the timer data TI of the corresponding address is sent to the timer calculator TE, and when the calculation of the timer calculator TE is completed, the timer data TO sent from the timer calculator TE is received. Store at the corresponding address. The compare / capture register CR receives the address CR from the instruction controller CTL.
Is received and the corresponding compare data CI is output to the timer calculator TE. When the capture flag CF is valid, the capture data CO is stored in the corresponding address. In general, compare and capture do not occur at the same time, so the address CA indicates both the address of compare data / capture data.

The timer arithmetic unit TE is a command controller CTL.
Calculation is performed based on the command COM from the terminal and the terminal state PI. For example, if the instruction COM counts up the timer data, the timer data TR to be counted up is sent from the timer register TR. Therefore, it is counted up and the timer data TO after the count-up is counted in the timer register TR. Send to. Also, the command CO
If M is an instruction to compare the timer data with the compare data, the timer data TI sent from the timer register TR and the compare data CI sent from the compare / capture register CR are compared, and the two data match. When that happens, an interrupt is issued to the CPU, for example. If the command COM is capture, the corresponding data is sent to the compare / capture register CR as capture data CO.

The input / output control unit IOC uses the terminal operation command I.
The OS sends a state PI of a specific external terminal to the timer arithmetic unit TE if it is an instruction to receive an external input, and outputs the calculation result PO of the timer arithmetic unit TE to a specific external if it is an instruction to output externally. Output to the terminal. Note that the terminal operation instruction IOS also includes a terminal number that identifies a terminal.

In such a conventional input / output control device, as described above, the timer register TR,
Only the bit width of the compare / capture register CR or the timer arithmetic unit TE can be calculated, and the original function or performance of the input / output device must be sacrificed in order to calculate the arbitrary bit width.

As shown in FIG. 1, the input / output control device of the present invention is obtained by adding a count control device CCT which is a third storage means to the input / output control device of FIG. The CCT temporarily stores the information OC such as the comparison result of the timer arithmetic unit and the overflow, and outputs the count-up enable signal EN if the extended instruction EX from the instruction controller CTL is valid.

FIG. 2 is a diagram showing an embodiment of this input / output control device, in which an overflow flag indicating that an overflow has occurred in the timer operation is stored in the count control circuit CCT. In the present embodiment, the count control circuit CCT is composed of a 1-bit register R and a logical product circuit A, the overflow flag stored in the register is valid, and the extended instruction EX from the instruction control unit CTL is valid. In such a case, their logical product becomes true, and the count-up enable signal EN
Is output to the timer calculator.

In the embodiment of FIG. 2, the information temporarily stored in the count control circuit CCT is only one kind of overflow flag. However, for example, two kinds of information of the overflow flag and the comparison result are When it is desired to use it in the operation of, the register of the counter control circuit CCT is prepared for each bit for each information, that is, a total of 2 bits are prepared as shown in FIG.
Also, 2 bits may be used so that valid / invalid can be instructed for each of the two pieces of information.

The input / output control device of this embodiment is
Since it is realized by adding necessary circuits based on the conventional input / output control device, the logical sum circuit () is added to the timer arithmetic unit TE so that the conventional count-up signal input from the terminal is also effective. (Not shown) is provided so that the count-up is continued when either the conventional count-up enable signal or the count-up enable signal output by the count control circuit CCT is valid. If there is no need for coexistence with such a conventional count-up enable signal, the circuits added to implement the input / output control device of the present invention are only a several-bit register and a logical product circuit. That is, it can be said that the increase in the size or cost of the hardware is infinitely equal to zero.

As described above, the input / output control device of the present invention is simply the addition of a simple circuit to the conventional input / output control device without interrupting the CPU and the original function of the input / output control device. It is possible to operate data of an arbitrary bit width without deteriorating performance or performance.

[Brief description of drawings]

FIG. 1 is a diagram showing an outline of an input / output control device of the present invention.

FIG. 2 is a diagram showing an embodiment of an input / output control device of the present invention.

FIG. 3 is a diagram showing an embodiment of a counter control circuit.

FIG. 4 is a diagram showing a conventional input / output control device.

[Explanation of symbols]

CCT count control circuit TR timer register MUXT timer register address decoder CR compare / capture register MUXC compare / capture register address decoder TE timer calculator IOC terminal input / output device CTL instruction control device PC program counter MUXP instruction address decoder MEM instruction storage device DEC instruction Code decoder R register A AND circuit

Claims (3)

[Claims] 1. An input / output control device for controlling input / output of input / output data, comprising: first storage means for storing timer data relating to the input / output control; and predetermined reference data relating to the input / output control. A second storage means for storing; a calculation means for performing an operation based on at least one of the timer data, the reference data, and the input / output data; and a third means for storing information related to the operation result of the operation. And a command control unit for sending a command relating to the calculation to the first, second and third storage units and the calculation unit, and when the calculation unit performs a predetermined calculation. , The third storage means is provided with a third storage means based on an instruction from the instruction control means.
By sending the information stored in the storage means to the operation means, when the operation means performs the operation, the information related to the operation result of the operation performed before the predetermined operation can be used. An input / output control device characterized by the above. 2. The input / output control device according to claim 1, wherein the information related to the calculation result includes information indicating that an overflow has occurred in the calculation. 3. The information according to the calculation result includes information indicating a comparison result when the timer data and the reference data are compared as the calculation. I / O controller.