JPS60195646A - Data processor - Google Patents

Abstract

PURPOSE:To shorten the time required for evacuating and restoring the content of registers, by providing registers composed of tag bits for storing unused conditions and evacuating the content of unused registers only at the time of interruptions, and then, restoring the content when the interruptions are terminated. CONSTITUTION:When an interruption is made from the outside during the operation, evacuation of operation registers RG1-RGn is started after the executing instruction is completed. A control section 1 reads out the content one bit by one bit while shifting a register 2 for reference and, when a tag bit is ''1'', outputs the content of a corresponding operation register to a bus 4 and put the content in the evacuating area of the memory 8. If the tag bit is ''0'', the control section 1 evacuates the content to the memory 8 when the tag bit in the next register is found to be ''1''. Therefore, only the content of operations registers being used is evacuated to the memory 8. When the interruption process terminated, data evacuated to the memory 8 are restored to the original registers by a return interrupt instruction.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a data processing technology and a technology that is effective when applied to a microcomputer system, such as a coprocessor that performs advanced data processing in cooperation with a microprocessor. Regarding effective techniques.

[Background Art] A coprocessor that works together with a microprocessor to perform advanced numerical calculations such as floating point calculations is provided with large-capacity registers in order to increase the calculation speed.

In a coprocessor or microprocessor that has such a large-capacity register, the contents of the register are saved to a memory save area when an interrupt occurs, and when the interrupt is recovered, the data that was saved to memory is restored to the original register. I need to do it.

Conventionally, in a coprocessor for floating point operations such as the Intel 8087, all data in a large 94-byte register was saved to a memory save area at the time of an interrupt (Intel 8087, August 1981). (Page 141-142 of "1APX86 Family User's Manual" published by Japan).

Therefore, it takes a considerable amount of time to save and restore the contents of the register at the time of an interrupt, so that as the register capacity increases, the interrupt reaction time becomes longer and the throughput of the entire system also decreases.

[Object of the Invention] An object of the invention is to shorten the time required to save and restore register contents at the time of an interrupt in a microprocessor or coprocessor having a large capacity register.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

In other words, this invention focuses on the fact that even if a coprocessor has a large capacity of registers, it will not use all the registers at the same time, and in most cases there will be a percentage of registers that are unused and idle. , a register consisting of tag pits is provided to memorize the used or unused state of each register, and when an interrupt occurs, only the contents of the register in use are saved while referring to this register, and after the interrupt ends, it is restored to the original register. By this,
The above object is achieved by omitting the time required to save the contents of unused registers, thereby shortening the time required to save and restore the entire register.

The present invention will be described in detail below along with examples.

[Embodiment] Fig. 1 shows an embodiment in which the present invention is applied to a microprocessor or coprocessor. It is formed on a single semiconductor substrate (chip) such as.

In the figure, 1 is the instruction register and the microprogram R.
This is a control section consisting of an OM or random logic circuit. Further, reference numeral 2 indicates work registers RG1, RG2, . . . . A reference register consisting of n dubits provided corresponding to each of RGn, and 3 an arithmetic logic unit (ALU) that performs operations such as addition, subtraction, squaring, and division.

The control unit 12 work registers RG1 to RGn.

The reference register 2 and the arithmetic logic unit 3 are connected to each other via an internal bus 4, and are also connected to external memories 7 and 8 etc. via external buses 5 and 6.
This constitutes a microcomputer system.

The memory 7 is made up of a read-only ROM (read-only memory) or a RAM (random access memory), and stores a program for operating the system. Further, the memory 8 is composed of a RAM or the like, and stores data necessary for the operation of the system or data obtained as a result of arithmetic processing.

When one of the working registers RG to RGn is selected by a control signal outputted from the control unit 1 and data is loaded into the selected register, the reference register 2 is configured to input data to the corresponding register 2 when data is loaded into the selected register. is set, and when data in a certain working register becomes unnecessary and is released, the corresponding dak bit is reset to rr - Orr. In addition, the above reference register 2
In this case, all the DAK bits can be reset simultaneously by a reset signal φr supplied from the outside to a reset terminal 9 provided on the chip.

Further, in this embodiment, a working register (RG
1 to RGn) is provided.

Next, the register saving and restoring operations when an interrupt occurs in the above system will be explained with reference to FIGS. 2 and 3.

The system executes instructions read from the memory 7 and fetched into the instruction register in the control unit 1 one by one, thereby performing desired work according to the program using the registers RG1 to RGn.

For example, when calculating the sum of data A and data B,
First, a signal designating a predetermined address in the memory 8 where data A is stored is output to the internal bus 4 in response to a command from the control section 1. As a result, the memory 8 is accessed and data A is read out, and the working register RG 1
-RGn, and at this time, a signal specifying the working register to be loaded is output from the control unit 1. Then, the gate of the corresponding working register is opened and data A is taken in, and the tag pit in the reference register 2 corresponding to that working register is set to da'1'I by the designated signal.

Similarly, when data B is read from memory 8 and loaded into another working register, the corresponding tag pit is set to "1". Thereafter, the contents of the register loaded with data A and B are supplied to the arithmetic logic unit 3, a desired operation is performed, and the result of the operation is held in one of the working registers RGs to RGn. . In this case as well, the tag focus in the corresponding reference register 2 is set to rr 1 rr.

However, when data in a work register becomes unnecessary during a predetermined work, the work register containing the data is released by a register release instruction of the program. In this case, the register is opened by resetting the bits 1- to "o" in the reference register 2 corresponding to the register.

The reference register 2 is reset by a reset signal φr supplied from the outside before the system starts operating, and all tag pits are reset to rr Ou.
~ has been. Therefore, when the tag pit corresponding to the working register to be used is set to 1'' as described above, and the register is released by setting it to 0'' when the data is no longer needed, each tag pit in the reference register 2 is exactly This indicates whether the corresponding work registers RG1 to RGn are used or not.

If the system is interrupted by an external interrupt request, a timer interrupt, or an internal interrupt request by software in the middle of a certain task, the saving of the task registers RG1 to RGn is started after the instruction being executed is completed. Ru.

At this time, the control unit 1 reads the contents (hereinafter referred to as tag word TW) bit by bit while shifting the reference register 2, and if the tag pit is rL I II, the contents of the corresponding working register are read out. The data is output to the internal bus 4 and stored in a predetermined save area (stack area) in the memory 8. On the other hand, the read tag pit is LL
In the case of OH, the corresponding working register is skipped and the tag pit of the next register is rr 1 rr or II
It is determined whether it is OH, and if it is "1", the contents are saved in the memory 8.

As a result, only the contents Dr2, Dr4, Dr6, . . . of the working registers in use are saved in the memory 8, as shown in FIG. Therefore, compared to the case where the contents of all work registers RG1 to RGn are saved, the time required for saving is significantly shortened. In addition,
The tag word TW in the reference register 2 is also saved to the memory 8 last.

Thereafter, an instruction to release all five working registers is executed to set all tag pins 1- of reference register 2 to II OH, and then the interrupt routine is executed.

On the other hand, when the interrupt processing is completed, the data saved in the memory 8 by a return interwoven instruction or the like is returned to the original working register. In this case, the recovery from the memory is carried out in a LIFO (last in first out) manner, and the tag word is first read from the memory 8 and loaded into the reference register 2. And the tag word TW
When the tag is restored, the reference register 2 is shifted by the control unit 1 and the tag pits are read out one by one, and at this time, a value (i') indicating the corresponding working register is set in the pointer 10. Ru. At this time, if the tag pit is 'bi', the next data read from the memory 8 is put into the working register indicated by the pointer 10.

On the other hand, when the read tag pit is '0'',
The value (i) of pointer 10 is skipped one by one, and when the tag pit reaches 1'', the next read from memory 8 is performed for the working register pointed to by pointer 10. I'll put in the data.

As a result, as shown in FIG. 3, the register data D r 1 g saved in the save area in the memory 8
D r 4 + D r 6... is the original working register RG 2. , , RG a , RG 5...
・You will be able to return to normality, speed, and power).

In the above embodiment, the greater the number of bits of the nine working registers or the total number of registers, the greater the effect of reducing register save and recovery time at the time of an interrupt.

Note that if the CPU shown in Figure 1 is a coprocessor for floating-point arithmetic, the coprocessor is usually configured not to have address output capability, so in that case, it will not be possible to perform the work in cooperation with the coprocessor. microprocessor (
The configuration is such that an address is output from the memory (not shown) and desired instructions and data are read from the memories 7 and 8.

[Effect] A register consisting of tag pits is provided to store the used or unused status of each working register, and when an interrupt occurs, only the contents of the register in use are saved while referring to this register, and the original register is restored after the interrupt ends. By doing so, the time required to save the contents of unused registers can be saved, and the time required to save and restore the entire working register can be shortened. As a result, the response to one interrupt request becomes faster, the response speed in real-time processing, multi-task processing, multi-user processing, etc. becomes faster, and the throughput of the system is improved.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

[Field of Application] In the above description, the invention made by the present inventor was mainly applied to microprocessors and coprocessors, which are the field of application that formed the background of the invention, but this invention is not limited thereto. This is useful for all data processing devices that have a large number of registers or bits.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to a microprocessor or coprocessor, FIG. 2 is an explanatory diagram showing a register saving method in the system, and FIG. FIG. 2 is an explanatory diagram showing a recovery method. 1...Control unit, 2...Reference register, 3...
... Arithmetic logic unit, 4... Internal bus, 5, 6.
...External bus, 7, 8...Memory, 9...Reset terminal, 10...Pointer, RG, ~RGn.
...Register (work register), Dr) ~ Drn...
...Register contents, φr...Reset 1-signal, TW
...tag word.

Claims (1)

[Claims] 1. In a data processing device equipped with a plurality of registers and capable of interrupt processing, a reference register consisting of a number of tag pits corresponding to each of the above registers is provided, and each of the above registers is The corresponding dak bit is set when executing an instruction to load data into a register, and the corresponding dak bit is set when executing an open instruction to open the data in each of the above registers when it is no longer needed. At the same time as being reset, only the contents of the register in use are saved to memory while referring to the DAK bit of the reference register mentioned above at the time of an interrupt, and at the time of recovery, the data in the memory save area is saved to the original while referring to the tag pit of the reference register. A data processing device characterized in that the data is loaded into a register. 2. At the time of an interrupt, the contents of the reference registers mentioned above are also saved to memory after the save of each register above is completed, and at the time of recovery, the contents of the reference registers that were saved are first loaded into the original registers. 2. A data processing device according to claim 1, wherein the data processing device comprises: