GB2156551A - Data processor - Google Patents

Abstract

A data processor has a plurality of registers (RG1, RG2 - - - RGn), a reference register 2 and a memory (8). In data processing, only those registers which are in use having tag bits entered on the reference register (2). In transferring the data of the plurality of registers (RG1, RG2 - - - RGn) to the memory (8), only the data of the registers with tag bits entered in the reference register (2) are transferred to the memory (8). In order to permit the data to be transferred from the memory (8) back to the respective registers, the data of the reference register (2) is also written into the memory (8). Since this arrangement is adapted to transfer only the data of those registers which have been in use, it permits a high-speed processing operation. <IMAGE>

Description

SPECIFICATION Data processor The present invention relates to a data processor for e.g. a microcomputer system. It may be used in a microprocessor or a coprocessor which cooperates with a microprocessor for performing large amounts of data processing.

A A microprocessor or coprocessor which, in cooperation with a microprocessor, executes a large number of numerical computations such as floating-point operations is provided with registers with a large total capacity in order to attain a high operating speed. In such microprocessor or coprocessor having registers of large capacity, it is necessary to save the content of the registers in the stack area of a memory during an interruption in processing and to return the data saved in the memory to the original registers when the interruption is over.

In a known coprocessor for floating-point operations such as, for example, '8087' produced by intel Inc., all the data of the registers having a large capacity of 94 bytes in total has to be saved in the stack area of a memory during an interrupt ("iAPX86 Family Users Manual" pp. 141-142, issued by Intel Japan in August 1981).

Therefore, a considerable time is required for saving and restoring the content of the registers when an interrupt occurs. This means that any increase in the capacity of the register prolongs the interrupt reaction time and also lowers the throughput of the whole system.

The present invention seeks to reduce this problem by providing a register in which the status of use of other registers are recorded.

This makes it possible to record only the contents of the registers which are in use at the time of the interrupt, so that no time is wasted in recording the contents of the register which are not in use.

The form of the data stored in the register may be tag bits from the other registers indicating whether or not they are in use.

An embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block diagram showing an embodiment in which the present invention is applied to a microprocessor or a coprocessor; Figure 2 is a diagram showing a method of saving registers in the system; Figure 3 is a diagram showing a method of restoring the registers in the system; and Figures 4, 5, 6 and 7 are program flow charts for explaining the operations of the processor in Fig. 1.

Fig. 1 shows an embodiment in which the present invention is applied to a microprocessor or a coprocessor. Parts enclosed with a chain line C in Fig. 1 form the microprocessor or the coprocessor, and they are formed on a single semiconductor substrate (chip) made of e.g. silicon.

In Fig. 1, a controller 1 has an instruction register, a microprogram ROM or random logic circuit, various registers to be described later, etc. The controller 1 is adapted to respond to interrupt signals which are supplied to a group of interrupt input terminals TIH. It is also adapted to deliver various control signals to a group of control terminals TC1 and to receive various control signals through a group of control terminals TC2.

The controller 1 may have a memory data register MDR and a memory address register MAR (neither of which is shown). The address data of external memories 7 and 8 are set in the memory address register MAR. Data to be written in the external memory 8 or data read out of the same are transferred to the memory data register MDR. Thus, the data of working registers (to be discussed in detail below), for example, are transferred to the memory 8 through the memory data register MDR. The data of the memory 8 are transferred to the working registers through the memory data register MDR. The installation of such memory data register MDR and memory address register MAR is intended to facilitate the control of the memory 8 by the controller 1.

Numeral 2 designates a reference register or tag register. The reference register 2 is composed of n tag bits provided in correspondence with the respective or n working registers Rug1, RG2, . . and RGn in which the data for use in operations etc. are held. The tag bits of the reference register 2 can be individually set or reset by the controller 1.

Though no special restriction is intended, all the tag bits can be simultaneously reset in accordance with a control by the controller 1.

The reference register 2 is further capable of a cyclic shift operation. That is, a feedback line L, as depicted is laid between the most significant bit and least significant bit of the reference register 2.

Shown at numeral 3 is an arithmetic-logic unit (ALU) which executes operations such as addition, subtraction, multiplication and division.

The controller 1, working registers RG1-RG#, reference register 2 an arithmeticlogic unit 3 are interconnected through an internal bus 4, and they are connected to the external memories 7 and 8, etc. through external bus lines 5 and 6. Thus, a microcomputer system is constructed.

In a case where the processor of this embodiment constructs the coprocessor, the groups of terminals TIH, TC1 and TC2 and the external bus line 6 are coupled to a main processor not shown. Thus, the processor in Fig. 1 can have its operation controlled by the main processor. Various data needed by the processor in Fig. 1 are applied from the main processor to the memory 8 through the external bus line 6 by way of example. When the memory 8 is accessed by the main processor, the use of the external bus line 6 by the processor in Fig. 1 is inhibited by, for example, a control signal which is supplied from the main processor to the group of terminals TC2. Since a method of controlling such system furnished with a plurality of processors is not directly pertinent to the present invention, the detailed description shall be omitted.Data processed by the processor in Fig. 1 are stored in the memory 8 though this is not especially restrictive. In this case, the processed data of the memory 8 can be referred to by the main processor through the external bus line 6.

The memory 7 is formed of a ROM (readonly memory) or a RAM (random access memory), and a program for operating the system is stored therein. The memory 8 is formed of a RAM or the like, in which data necessary for the operation of the system, data resulting from arithmetic processing, etc. are stored.

Each tag bit of the reference register 2 is set to "1" when the corresponding one of the working registers RG,-RGn is selected by a control signal delivered from the controller 1 so as to load the selected register with data, whereas it is reset to "0" responsively when the data of the corresponding working register become unnecessary and are released. In addition, all the tag bits of the reference register 2 2 can be reset by the controller 1, and they can be simultaneously reset in response to a reset signal fr which is externally supplied to a reset terminal 9 mounted on the chip.

Further, this embodiment is provided with a pointer 10 which is controlled by a control signal from the controller 1 and which points to the working register (RG1-RGn) to be loaded with data read out of the external memory 8. The data i of the pointer 10 are set by the controller 1. They can also be referred to by the controller 1.

In the illustrated system, the program stored in the memory 7 is run as follows.

Instructions fetched from the memory 7 into an instruction register within the controller 1 are excuted one by one. The registers RG,-RGn are used in a desired job or process conforming to the program.

For example, in a case where the sum between data A and data B is to be evaluated, a signal which designates the predetermined address of the memory 8 storing the data A is first output to the internal bus 4 by a command from the controller 1. Thus, the memory 8 is accessed to read out the data A, with which one of the working registers RG,-RGn is loaded. At this time, a signal which designates the working register to be loaded is output from the controller 1. Then, the gate of the corresponding working register is enabled, and the data A read out from the memory 8 is loaded into the working register. Simultaneously, the tag bit of the reference register 2 corresponding to the working register is set to "1" by the designating signal.

Likewise, the data B is read out from the memory 8 and is loaded into another working register. Simultaneously, the corresponding tag bit is set to "1". Thereafter, the contents of the registers loaded with the data A and B are supplied to the arithmetic-logic unit 3 in which the desired operation is executed, and the operated result is input to one of the working registers RG1-RGn Also on this occasion, the corresponding tag bit in the reference register 2 is set to "1".

Meantime, when data in a certain working register has become unnecessary midway of a predetermined job, the working register containing the data is released by the register release instruction of the program. In this case, the release of the register is effected by resetting the tag bit of the reference register 2 corresponding to the register to "O".

The reference register 2 is reset by the externally supplied reset signal , so as to assume "0" at all the tag bits before, for example, the start of the operation of the system. As will be described later, the reference register 2 may well be reset by the controller 1.

As stated above, the respective tag bits are set to "1" when the corresponding working registers are used. On the other hand, the tag bit is reset to "0" responsively when data in the working register corresponding thereto has become unnecessary or unused. That is, the register is released. In this manner, the respective tag bits of the reference register 2 exactly express the used or unused statuses of the corresponding working registers RG,-RGn.

Next, the saving and restoring operations of the registers in the case of an interrupt will be described with reference to Figs. 2 and 3.

When an external interrupt request or a timer interrupt request has been made through the group of external terminals TIH or an internal interrupt request based on software has been made through the external bus line 6 in the course of a certain job or process, the saving of the working registers RG,-RGn is started after an instruction under execution ends.

In this case, the controller 1 reads out the content (hereinbelow, termed "tag word TW") every bit while shifting the reference register 2. In a case where the tag bit is "1", the content of the corresponding working register is delivered to the internal bus 4 and is put into a predetermined stack area in the memory 8. In contrast, in a case where the tag bit read out is "0", the corresponding working register is jumped, whereupon whether the tag bit of the next register is "1" or "0" is checked, and the content thereof is saved in the memory 8 subject to the tag bit being "1 ".

Thus, only the contents Dr2, Dr4, Dr5 .....

of the working registers having been in use before the start of the interrupt operation are saved in the memory 8 as illustrated in Fig. 2.

Therefore, a period of time required for saving is sharply shortened as compared with that in the case of saving the contents of all the working registers RG,-RGn. The tag word TW in the reference register 2 is also saved in the memory 8 at last.

Thereafter, an instruction for releasing all the working registers is executed to bring all the tag bits of the reference registers 2 to "0", whereupon an interrupt routine is executed.

Meanwhile, when the interrupt processing is over, the data saved in the memory 8 are returned to the original working registers by a return interrupt instruction or the like. The restoration of the data from the memory 8 in this case is effected as follows. First, the tag word TW is read out of the memory 8 in accordance with the LIFO (last-in first-out) system, and it is loaded into the reference register 2. When the tag word TW has been returned in this manner, the reference register 2 is operated to shift by the controller 1, and the tag bits provided from the reference register 2 are loaded into the controller 1 one by one. On this occasion, the value (i) indicative of the corresponding working register is simultaneously set in the pointer 10. When the tag bit read out is "1", the data read out of the memory 8 is input to the working register indicated by the pointer 10.

On the other hand, when the tag bit read out is "0", the control proceeds while skipping over the corresponding value (i) of the pointer 10, whereupon when the tag bit has subsequently assumed ''1", the working register indicated by the pointer 10 at that time is supplied with the data subsequently read out of the memory 8.

Thus, as illustrated in Fig. 3, the data Dr2, Dr4, Dr5 ..... of the registers saved in the stack area of the memory 8 are correctly and quickly returned to the original working registers RG2, RG4, RG5, .. . respectively.

With the embodiment, the effect of shorten- ing the periods of time for saving and restoring the registers at the time of the interrupt becomes greater as the number of bits of the working register or the total number of the registers increases more.

Now, the operation of the processor in Fig.

1 will be described more in detail with reference to program flow charts in Figs. 4 to 7.

First of all, a program as shown in Fig. 4 is run upon closure of a power supply or upon start of the system operation before an ordinary program is run.

A decision process step P1 decides if an instruction fetched in the instruction register within the controller 1 is an instruction RESET instructing the reset of the reference register or tag register 2. Unless the instruction is the reset instruction, a similar decision is repeated again. If the instruction is the reset instruction, a reset or initialize process P2 is subsequently executed. Thus, all the tag bits of the tag register 2 are reset to "O". The execution of the process P2 is followed by the run of the ordinary processing program.

The reset of the tag bit, namely, the release of the working register is effected as follows.

First, an instruction is decoded at a processing step P3 as shown in Fig. 5. Next, a decision process P4 decides whether or not the instruction is a tag bit reset instruction namely, tag bit free instruction FREE. If the instruction is the reset instruction FREE, a process P5 is executed.

Owing to the execution of the process P5, a variable i designated in the reset instruction is set in the pointer 10 in Fig. 1. When the next process P6 is performed, one of the tag bits of the tag register 2 designated by the variable i is reset to "O".

If it is decided by the decision process P4 that the instruction is not the reset instruction, the former instruction is executed.

The working registers RG,-RGn are saved as follows.

As indicated in processes P7 and P8 in Fig.

6, address data An designating the proper address of the external memory 8, and a variable jare set in the adequate registers of the controller 1, while the variable i within the pointer 10 in Fig. 1 is set at zero. Although not especially restricted, the value k of the variable j is rendered n equal to the number of the working registers RG1-RG,,.

Subsequently, the variables i and j are compared by a decision process P9. If the variable i is not greater than the variable j, in other words, if all the tag bits of the tag register 2 have not been referred to, a decision process P10 is subsequently performed.

The decision process P10 checks the value of that tag bit of the tag bits of the tag register or reference register 2 which is indicated by the variable i. If the tag bit referred to is "1", in other words, if the working register corresponding to the tag bit was in use before the interrupt processing, a series of succeeding processes P11 to P16 are executed.

More specifically, at the process P1 1, data in the working register RG, designated by the pointer 10 is transferred to the memory data register MDR in the controller 1, and at the process P12, the address data A, indicative of the address of the memory 8 is set in the memory address register MAR in the controller 1.

At the next process P13, the data in the memory data register MDR is written into the memory address Dr, of the memory 8 desig nated by the memory address register MAR.

That is, the data of the working register RG, is saved in the memory 8.

At the subsequent process P14, the address data A, is incremented by 1 (one). That is, the address data A, comes to indicate the next address of the memory 8. At a process P15, the variable i in the pointer 10 is incremented by 1 (one). That is, the variable i in the pointer 10 comes to have a value pointing to the next working register.

At the process P16, all the tag bits of the tag register 2 are shifted by one bit. Thus, the controller 1 is supplied with the next tag bit data.

After the process P16, the process P9 is performed again.

If the tag bit referred to is "0" at the decision process P10, in other words, if the working register corresponding to the tag bit was not in use, the processes P 1 5 and P 1 6 are immediately executed. That is, the variable i is updated, and the shift operation of the tag register 2 is conducted. In this case, the processes P11 - P13 for saving the working register and the process P14 for updating the address data are not executed.

Owing to such repetition of the processes P9-P16, only the working registers designated by the tag bits in the tag register 2 are saved in the memory 8.

When the number of times of reference to the tag bits exceeds the number of bits of the tag register 2, the execution of the decision process P9 is followed by a process P17. At the process P17, the address A, of the memory 8 in which the tag register 2 is to be saved is set. Next, at a process P18, all the tag bits of the tag register 2 are written into the memory data register MDR in the controller 1, and at a process P19, the address data is written into the memory address register MAR. At the subsequent process P20, the data of the memory data register MDR, namely, the tag bit data is written into the memory 8. The execution of the process P20 ends the run of the register saving program.

The restoration of the working registers RG,-RG, after the end of the interrupt processing is effected as follows.

As shown in Fig. 7, a process P21 is first executed at which the address data A, indicating one of the addresses of the memory 8 storing the tag bit data is set in the proper register in the controller 1. Next, a process P22 is performed to write the address data A, into the memory address register MAR. The tag bit data written in the memory 8 is written into the memory data register MDR by the execution of a process P23, and the tag bit data of the memory data register MDRa is written into the tag register (reference register) 2 by the execution of a process P24. That is, the necessary tag bit data is restored in the tag register 2 by the execution of the processes P21-P24.

Next, at a process P25, the address data A, corresponding to the first working register is set in the proper register in the controller 1, and at a process P26, the variable i of the pointer 10 is rendered zero and the variable j is set in the proper register in the controller 1.

The value k of the variable j is the value n corresponding to the number of the working registers RG1-RG,.

Next, a decision process P27 is performed.

If the variable i set in the pointer 10 is not greater than the variable j, a decision process P28 is performed.

If it is decided at the decision process P28 that the tag bit is "1", a series of ensuing processes P29-P34 for restoring data are executed.

More specifically, at the process P29, the address data A, of the memory 8 is set in the memory address register MAR, and at the process P30, data in the address of the memory 8 designated by the memory address register MAR is written into the memory data register MDR. Owing to the execution of the process 31, the data of the memory data register MDR is written into the working register RG, designated by the pointer 10.

The process P32 increments the address data A, by 1 (one). That is, the address to be subsequently referred to among the plurality of addresses of the memory 8 is set in the register in the controller 1.

The process P33 increments the variable i in the pointer 10 by 1 (one).

When the process P34 is executed, all the tag bits of the tag register 2 are shifted by one bit. Thus, the tag bit data to be subsequently referred to is supplied to the controller 1.

If it is decided by the decision process P28 that the tag is "0", the processes P29-P32 for the data restoration are not executed. In this case, the process P33 for updating the variable i and the process P34 for the shift operation are immediately executed.

After the process P34, the decision process P27 is executed again.

Owing to such repetition of the processes P27-P34, only the data of the working registers having been in use before the start of the interrupt processing are respectively restored.

When all the tag bit data restored in the tag register 2 have been referred to, the run of the program for the data restoration ends.

In a case where the CPU shown in Fig. 1 is a coprocessor for floating-point operations, the coprocessor is usually constructed so as to have no address output ability though not especially restricted. In that case, the system is so constructed that addresses are output from a main processor such as a microprocessor (not shown) for performing jobs in cooperation with the coprocessor, to read out desired instructions and data from the memories 7 and 8.

According to this invention, the following effects are attained.

A register which is composed of tag bits for storing the used or unused statuses of respective working registers is disposed, only the contents of the registers in use are saved while the tag register is being referred to at the time of an interrupt, and the save contents are returned to the original registers after the end of the interrupt, so that a period of time otherwise required for saving the contents of the registers not in use can be dispensed with, thereby to shorten a period of time required for saving and restoring the working registers as a whole. In consequence, a reaction to an interrupt request quickens to bring forth the effects that reaction speeds in realtime processing, multi-task processing, multiuser processing, etc. are increased and that the throughput of a system is enhanced.

While, in the above, the invention made by the inventor has been concretely described in conjunction with an embodiment, it is needless to say that the present invention is not restricted to the embodiment but that it can be variously modified within a scope not departing from the subject matter thereof. By way of example, it is also allowed to set the tag data of the reference register 2 in the head address of the stack area of the memory 8 and to set the data of the registers RG,-RGn in addresses next the head address. Since, in this case, the tag data is set in the head address of the stack area, processes for saving and restoring the register data are facilitated.

In the case where the reference register 2 is capable of shifting as in the embodiment, the internal arrangement of the controller 1 can be simplified much. However, the shifting of the reference register 2 is not needed when the controller 1 is adapted to directly refer to the bits of the reference register 2.

Whether or not the memories 7 and 8 are disposed outside the processor C is not essential to this invention. If necessary, these memories 7 and 8 may well be formed on a single semiconductor substrate along with the processor C by integrated circuit technology.

In the above description, the invention made by the inventor has been chiefly explained on cases of applying it to a microprocessor and a coprocessor which form the background field of utilization thereof. However, this invention is not restricted thereto, but it can be utilized for any data processing equipment in which the number of possessed registers or the number of bits thereof is large.

Claims (12)

1. A data processor comprising: a controller, a plurality of first registers which are re spectively accessed by the controller, and a second register in which data indicating respective statuses of use of the plurality of first registers are set.

2. A data processor according to Claim 1, having a memory, in which the controller is arranged to be capable of a first control operation of accessing the respective first registers and setting in the second register the data corresponding to the accessed ones of the first registers, and a second control operation of transferring only the data of those of the first registers designated by the second register to the memory by referring to the second register.

3. A data processor according to Claim 2, wherein the controller is arranged to be further capable of a third control operation of transferring the data transferred to the memory, to only those of the first registers designated by the second register.

4. A data processor according to Claim 3, wherein the controller is arranged to be capable of a fourth control operation of transferring the data of the second register to the memory.

5. A data processor according to Claim 3 or Claim 4 further comprising: a pointer which is controlled by the controller and which points to the respective first registers, the pointer designating the respective first registers which require the transfer of the data in the second and third control operations.

6. A data processor according to any of Claims 3 to 5 wherein the controller is capable of interrupt processing, and the second control operation is executed before execution of the interrupt processing, while the third control operation is executed after end of the interrupt processing.

7. A data processor according to any one of Claims 3 to 6 wherein the second register is capable of shifting, and it is shifted in the second and third control operations.

8. A data processor according to any one of Claims 2 to 7 wherein the unit data to be set in the second register can be respectively initialized by the controller.

9. A data processor according to any one of preceding claims further comprising: control lines which are laid between the controller and the plurality of first registers respectively, the respective data of the second register being set by control signals which are applied from the controller to the control lines.

10. A data processor comprising: a controller, a plurality of first registers which are respectively accessed by the controller, and a second register in which data designating those of the plurality of first registers requiring data transfer are set.

11. A data processor according to Claim 10, wherein the data of the second register are set by control signals provided from the controller.

12. A data processor substantially as herein described with reference to, and as illustrated in the accompanying drawings.