JP2001286189A - Motor controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a an inexpensive motor controller capable of reducing the load of CPU and reducing the capacity of a memory for storing the drive data table of a motor. SOLUTION: Speed data for setting the speed of the motor from the speed table memory in stage are successively read by a memory access control part 1001 without interposing the control of CPU controlling the whole drive control of the motor, data values read from the speed table by a time conversion circuit 1002 are converted into time data, and a phase changeover signal for operating the motor by a phase signal generating part 1003 is generated on the basis thereof. Generation of access to a next memory table for a memory access control part 1001 is promoted every the prescribed number-of-times of the time data of a time conversion means 1002, and theretofore the time conversion means is operated by using the same data values read from the speed table.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor control device, and more particularly to a motor control device for controlling driving of a motor controlled by a combination of a plurality of phase signals.

[0002]

2. Description of the Related Art Conventionally, a motor (stepping motor) controlled by a combination of phase signals has been used as a driving means for a paper feed mechanism or the like as a power source for conveying paper or the like of a printer or the like.

FIG. 2 shows the structure of a motor control unit for controlling the above-described motor in a conventional image forming apparatus or the like. In FIG. 2, reference numeral 2001 denotes a CPU for controlling a series of operations, and 2002, a system bus. Each component is connected to the system bus. Reference numeral 2003 denotes a ROM of the CPU, which stores programs and various data.

Reference numeral 2004 denotes a data RAM, 2005 denotes a timer IC, 2006 denotes an interrupt signal from the timer IC, 2007 denotes a phase pattern signal for operating the motor, 2008 denotes a buffer circuit for interfacing with the motor, and 2009 denotes a motor. is there.

[0005] The CPU 2001 receives an interrupt from the timer IC at fixed time intervals,
Based on the drive data developed in the AM 2004, the phase pattern signal of the motor 2009 is controlled via a bus interface circuit and a buffer circuit including an amplifier. That is, the drive data is read out and transferred to the buffer circuit 2008 under the control of the CPU 2001 itself.

FIG. 3 shows the operation timing of the motor in FIG. Here, the motor 2009 receives the signal A
And the signal B is operated by a combination of two phase signals.
By giving the state from 1 to T4, it is possible to rotate by a predetermined angle. (Return to T1 after T4).

FIG. 4 shows the state of acceleration and constant speed rotation of the motor controlled by the conventional configuration of FIG. FIG. 4 is a graph of motor speed and time. As shown in the figure, by switching the phases at times t1, t2,..., The control gradually changes from a slow speed to a fast speed. At the same speed. Generally, this type of motor requires a high torque at the start of rotation, so it starts operating at a low speed,
It is required to gradually switch to high-speed operation.

As shown in FIG. 3, the rotation angle of the motor due to the change in the state of the phase signal is constant. Therefore, by shortening the period of the phase signal applied to the motor, T1 If T2, T3, and T4 are switched earlier, the motor will rotate at a higher speed as a result.

The lower part of FIG. 4 specifically shows motor speed control by phase switching. For example, at a certain time tn, the motor phase signal is switched from T1 to T2 in FIG. It can be seen that the time until each phase signal is switched gradually decreases by repeating the operation of switching from T3 to T3.

Here, referring to FIG. 2 again, a conventional method of controlling the motor speed will be described.

When operating the motor 2009 in accordance with an instruction from an operation panel (not shown), the CPU 2001 shown in FIG.
003) Prepare above. The phase signal supplied to the motor is obtained by converting the output signal of the CPU into an interface circuit 2008
, A pattern of T1 is given to the motor 2009 via the.

Then, an operation start command is given to the timer 2005 to set the first value of the driving data table. After that, the operation of the timer 2005 causes an interrupt 2006 to the CPU 2001. Upon receiving the interrupt, the CPU 2001 rewrites the phase signal to the motor 2007 to T2 and reads the value of the next table from the RAM of 2004.
The timer 2005 is set. By repeating this operation sequentially, the update of the timer is stopped when the predetermined speed is reached, and thereafter, the constant speed drive is started by only updating the phase signal pattern. The operation of FIG. 4 is realized by the above operation.

[0013]

However, in the above-mentioned conventional configuration, the CPU based on the interruption from the timer IC is used.
Since the phase signal is switched under the initiative of the above, there are the following problems.

1) Time delay of phase signal switching timing Except in the case where a time delay occurs from the interruption to the setting of the signal, and the phase switching time is sufficiently large with respect to the interruption processing time, so that there is no problem. In general, there is a problem that the rotation speed varies.

2) Decrease in CPU processing speed due to interruption When there are a plurality of motors or when the rotation speed of the motor is high, the interval between interruptions inputted to the CPU becomes short, and C
A disadvantage occurs in that the other processing efficiency of the PU is deteriorated.

3) Increase in table memory In a system that requires a plurality of acceleration / deceleration characteristics of the motor, the value of the table increases and the cost increases.

An object of the present invention is to provide a motor control device of this type which can be implemented simply and inexpensively, can reduce the load on the CPU as control means, and reduce the capacity of a memory for storing a motor drive data table. To be able to do it.

[0018]

According to the present invention, there is provided a motor control device for controlling the driving of a motor controlled by a combination of a plurality of phase signals. A speed table memory for storing speed data to be set dynamically, a memory access control unit for sequentially reading the data of the speed table without the control of a CPU for controlling the entire drive control of the motor, and a read from the speed table Time conversion means for converting the converted data value into time data, a phase signal generation unit for generating a phase switching signal for operating the motor based on the output of the time conversion means, and a predetermined number of times of the time conversion means Prompts the memory access control unit to generate access to the next memory table for each data output; Employing the configuration provided with the interval control means for controlling so as to operate said time conversion means using the same data values read from degrees table.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIGS. 1 and 7 show a motor control circuit according to an embodiment of the present invention. FIG. 7 shows the overall configuration of a motor control circuit to which the present invention is applied.
FIG. 1 shows a part thereof, in particular, the configuration of a motor control block unit in detail.

In FIG. 7, reference numeral 7001 denotes a CPU for controlling a series of operations.
The drive control of the motor is performed in accordance with a program stored in the ROM 7002, with 03 as a work area.

In FIG. 7, three motors (M) used as power sources for paper feeding of a printer are provided, and are controlled by motor control blocks 7004 to 7006, respectively.

In this embodiment, the CPU 7001 does not directly control input / output of motor drive data. The input and output of the motor drive data is performed by the motor control block 7004 described above.
To 7006, and a bus arbitration circuit (bus arbiter) 70
07. The bus arbitration circuit 7007 converts the speed table data from the motor control block into a DM
This is for accessing by A (Direct Memory Access) control.

FIG. 1 shows the motor control block 7004 described above.
The detailed structure around ~ 7006 is shown.

In FIG. 1, reference numeral 1000 denotes a motor control block corresponding to the motor control blocks 7004 to 7006 in FIG. In FIG. 1, reference numeral 1001 denotes a DM
A memory access control unit constituted by an AC (DMA controller); 1002, a time conversion circuit constituted by a timer circuit; 1003, a phase signal generation unit for generating a motor phase signal (detailed configuration will be described later);
004 is a speed table storage memory (for example, R
A bus arbitration circuit for accessing the OM 7002 or the RAM 7003).

In this embodiment, motor drive data, that is, speed table data, is not controlled by the CPU 7001 but is performed by the motor control block 1000 and the bus arbitration circuit 1004.

Reference numeral 1005 denotes a timer circuit for generating an interrupt at an arbitrary rotation step, which is used for the motor drive control of the CPU 7001.

Reference numeral 1006 denotes an interval register for controlling how many times a signal from the time conversion circuit constituted by the timer circuit 1002 is received before requesting the memory access circuit 1001 to start DMA.

That is, in this embodiment, the data sequentially read from the speed table memory by the memory access control unit 1001 via the bus arbitration circuit 1004 is loaded into the time conversion circuit 1002 (“CMP”).
Signal), and every time the time conversion circuit 1002 completes time measurement, generates a “PPS-CLK” signal to the phase signal generation unit 1003 to generate a phase switching signal.

When prompting the memory access control unit 1001 to read the next data, the interval register 1006 is operated to mask the request to the memory access control unit 1001 up to the number of times set in the interval register 1006. As a result, the same drive data can be used a plurality of times, and the memory capacity for storing the motor speed table can be reduced.

FIG. 12 shows an example of the motor speed table. The speed table storage memory of FIG.
And continues to 162, and the data at the right end in the figure is stored at each address. The left side of the figure is not the actually stored data, but the actual accumulated driving time, control speed (PPS), acceleration (PP) corresponding to each data in a certain drive system.
S / ms) and the drive time (ms). In this example, the initial speed is 220 PPS and eventually 294
The motor is controlled to reach 1 PPS.

FIG. 5 is a graph of the table shown in FIG. 12. As shown, this operation accelerates the motor at a constant acceleration, and the acceleration is a horizontal straight line, and the speed is a linear line with a constant inclination. Change above. Further, in order to configure such a driving condition, it is understood that the interval of the phase switching of the motor is long immediately after the start, and it is necessary to control so that the interval is gradually shortened.

In the example of the table in FIG. 12, all the data under a certain drive control condition are arranged. As is clear from FIG. 12, the data in this table is almost identical between adjacent data (time values). Are the same or very similar values. Therefore, the previous interval register 10
If the value of 06 is set to 2 and the same data is used twice, DMA
If masking is performed so that a request occurs, it is only necessary to store time data for two times in the table, and the capacity of the table memory can be reduced.

Next, the operation in the above configuration will be described in detail.

When the motor is started by the CPU 7001 in FIG. 7, drive data is loaded in the speed table storage memory. In this case, as described above, on the premise of the control of the interval register 1006, data is created so that one data can be used twice (or the number of times corresponding to the set value of the interval register). Shall be used.

FIG. 13 shows an example of a speed table that can be used in the configuration of FIG. This speed table is 612 from 96 PPS to 11 STEP.
This is an example of a speed table that accelerates to PPS, and can be used by storing “2” in the interval register 1006. FIG. 9 shows an acceleration characteristic graph when the speed table of FIG. 13 is used.

The white graph of FIG. 9 shows the operation when the motor is driven without using the control of the interval register 1006 with the data of FIG. 13, and the black graph shows the operation of the interval register 1006 in this embodiment. The operation when the motor is driven using the control is shown. FIG.
It can be seen that the same data is used twice for all phase switching (except for the first phase switching).

Therefore, according to the control of this embodiment,
The capacity of the memory required for the speed table can be reduced to almost half as compared with the conventional method in which the same resolution is controlled.

The cumulative driving time shown in FIG. 13 shows the case where the motor is driven without using the control of the interval register 1006. The actual cumulative driving time is as shown in FIG. It is twice as large.
The acceleration is halved in FIG. 9 for the same reason. Therefore, when the motor control is actually performed using the configuration of FIG.
It is necessary to create each data so as to satisfy the cumulative driving time and acceleration actually required in accordance with the value given to.

Assuming that the speed table as described above is prepared, the CPU first sends a start address (START ADDRESS in FIG. 1) and an end address (END ADDRESS in FIG. 1) to the memory access control unit 1001 of the CPU 1001. Is set.

Subsequently, the memory access control unit 1001 reads the data at the first address (address 100 in the example of FIG. 12) by using the bus arbitration circuit 1001.
4 is an address signal and a request signal “DREQ”.
Output a signal.

Thus, the bus arbitration circuit 1004 performs timing arbitration with a memory access request from another motor control unit, outputs data to the memory access control unit 1001 when data of the requested address is read, and outputs data to the memory access control unit 1001. Is output as a signal "DACK" for notifying the determination of.

Thus, the memory access control unit 100
1 outputs the read speed table data as a “CMP” signal to a time conversion circuit 1002 including a timer circuit.

Thereafter, when it is time to actually operate the motor, "CL" is input to the time conversion circuit 1002.
The R ″ signal is turned off, and the memory access control unit 1001
, A "DMA-EXEC" signal indicating a start is input.

As a result, when the internal counter of the time conversion circuit 1002 operates and reaches the value input by the "CMP" signal, the signal "PPS-CLK" is output to the phase signal generator 100.
Enter 3 This signal "PPS-CLK" is also input to the memory access control unit 1001 via the interval register 1006. As described above, the interval register 1006 outputs the signal "PPS-
−CLK ”is input to the memory access control unit 1001.

That is, the interval register 1006
Is set to “2”, the output of “PPS-CLK” to the memory access circuit 1001 is allowed to proceed to the next table data when two PPSs occur.
Thus, the number of occurrences of DMA with respect to the number of occurrences of “PPS-CLK” is controlled.

In other words, the interval register 1006 allows the memory access circuit 100 of “PPS-CLK”
If masked on input to 1, the next "PPS"
-CLK "also occurs at the timing generated by the same table data as the previous time.

Then, the interval register 1006 sends the memory access circuit 1001 a second "PPS-CL"
K ", the memory access control unit 100
1 inputs the value read by the second memory access to the time conversion circuit 1002 as a “CMP” signal in response to the input of “PPS-CLK”, and also inputs the value to the bus arbitration circuit 1004 to perform the third memory access. Outputs a predetermined signal.

By continuing the above operation, "PPS-CLK" which is the phase switching signal of FIG. 4 is generated based on the speed table of FIG. 13, and finally reaches the address of the table memory, and the value of PPS is changed. When the memory access control unit reaches 612 PPS, the memory access control unit 1001 terminates the subsequent memory access and an interrupt signal “DMA-END” indicating that the motor acceleration operation has been completed.
And notifies the CPU 7001. Also, TCU1
Reference numeral 005 notifies the CPU that the motor has advanced an arbitrary rotation angle from an arbitrary time, and the CPU 7001 performs predetermined motor control based on the notified rotation angle.

As described above, the motor can be accelerated based on the speed table by controlling the generation interval of "PPS-CLK" to be gradually shortened.

Next, a configuration for generating a motor control signal based on "PPS-CLK" will be described. Here, the motor of the present embodiment is “A”, “A−”, “
B "and" B- ".

FIG. 6 shows the configuration of the phase signal generator 1003 for generating the phase signal of the motor shown in FIG. 1 in detail. In FIG. 6, "A", "A"
-Registers 6001 to 600 for storing pattern data for signals of each of the four phases ",""B" and "B-"
4

In FIG. 6, reference numeral 6005 denotes a counter, which operates every time "PPS-CLK" is input.
According to the output value of the counter, a corresponding bit value in the register is output to be a phase signal. Counter 6
In 005, the direction of advance of the phase signal pattern can be reversed by switching between UP and DOWN, thereby controlling the rotation direction of the motor.

When there are eight combinations of motor phase signals, the registers 6001 to 6004 are 8-bit registers (A [0] to A [0] in the case of the illustrated register 6001).
REG [0] → REG [1] → REG [2] → REG
[3] → REG [0] operates, and at the time of DOWN count, REG [0] → REG [3] → R
EG [2] → REG [1] → REG [0] (“REG” is a register A [0] to A [A] in FIG. 6).
[3], and in the case of the B phase, B [0] to B [3]). The output signal is output to one of the excitation phases of the motor via a 4-in-1 multiplexer.

By configuring the phase signal generator 1003 as described above, the interval register 1006 is provided. Even if only a single speed table is provided, various acceleration patterns of each motor can be obtained. Can be generated.

Although only the acceleration operation has been described above, if a speed table for deceleration is prepared,
It goes without saying that the deceleration operation can be controlled with the same configuration. For example, FIG. 10 shows operations from start-up to acceleration to constant speed operation to deceleration to stop of the motor. Here, the DMA is started to read the speed table of the acceleration setting in order to start the acceleration operation, and when the DMA end interrupt occurs, the motor rotates at a constant speed, and it is necessary to decelerate to stop. At this time, the CPU 7001 starts DMA for reading the deceleration table. Then, a DMA termination interrupt generated when the deceleration table is terminated causes a CPU termination.
Reference numeral 7001 can detect that the rotation of the motor has reached the minimum speed.

FIG. 11 shows a more complex composite operation. For example, in a printer or the like, in the motor control in the paper conveyance, it is normal that a plurality of motors are provided in the paper conveyance system, and in such a configuration, the paper being conveyed may be bitten by another motor. However, the motor is not only restricted by its own drive specifications, but also by other motors. In such a configuration, it is necessary to perform more complicated drive control as shown in FIG.

For example, in FIG.
In the acceleration phases of t1, t2 and t3, different speed data tables are used to obtain different accelerations. This is because the motor can only be rotated up to the medium speed immediately after the start due to the balance with other motors, and the acceleration speed itself must be low in the first acceleration at t0 to t1. Thereafter, at the time (t2) when the paper is released from the restriction of the slow motor, the speed is increased to high speed using another speed table and the desired constant speed operation (t3 to t) is performed.
Is performed, and from the timing t4, the operation is stopped using the table for deceleration.

As is apparent from the above, according to the present embodiment, the memory access control unit 1001 accesses the speed table memory independently of the control of the CPU 7001 that controls the entire motor drive control. Therefore, the load on the CPU 7001 can be reduced, the data read from the speed table memory is loaded into the time conversion circuit 1002, and the access to the next memory table is urged in accordance with the interval register 1006. , So C
There is an excellent effect that the load on the PU can be reduced, a plurality of acceleration / deceleration patterns can be generated from a single table, and the memory capacity required for the speed table memory can be greatly reduced.

If there are a plurality of motors to be controlled, a bus arbitration unit is provided to arbitrate memory access so that the same speed table memory can be shared by a plurality of motors. The load on the CPU can be reduced.

Further, the phase signal generator 1003 is configured to sequentially switch and output the contents of a register having a length capable of expressing a combination of phases for controlling the motor as a motor control signal to the CPU, thereby providing the CPU with a signal. Load can be reduced.

(Second Embodiment) FIG. 8 shows the overall configuration of a different motor control system according to the present invention. FIG.
Is connected to a dedicated bus 8000a independent of the system bus 8008 of the motor control unit 8000, and a bus for transferring motor data is connected to the CPU 800.
This is independent of the system bus 8008 on one side.

In FIG. 8, reference numeral 8001 denotes a CPU for controlling a series of operations.
ROM 8002 in which programs and data are stored,
A RAM 8003 used for processing of the CPU 8001 is connected.

On the other hand, reference numeral 80 on the motor control unit 8000 side
Reference numerals 04 to 8006 denote motor control blocks corresponding to the motor control block 7004 (or 1000 in FIG. 1) in FIG. 7, respectively. Reference numeral 8007 denotes speed table data from the motor control blocks 8004 to 8006 as D.
This is a bus arbitration circuit for accessing by MA transfer, and is connected to a RAM 7008 storing a speed table via a dedicated bus 8000a.

As described above, by providing the speed table memory on a dedicated bus independent of the system bus of the CPU that controls the entire system, no load is imposed on the system bus when DMA occurs, and the overall system performance is reduced. Can be improved as compared with the first embodiment.

Each motor control block 7004 to 7 in FIG.
006 can be configured in the same manner as in the above-described first embodiment, and the internal configuration and operation are the same as those described above, and will not be described here.

In both the first and second embodiments, the size of the pattern register is prepared by the number of motor phase patterns to be used. In the above embodiment, 4 bits, that is, four types of motor phase patterns are used. However, it goes without saying that the bit length may be 8 or 16, and does not impose any restrictions on the present invention.

In the above description, the motor has been described on the assumption that the motor is used for feeding paper in a printer or the like. However, the motor control according to the present invention is not limited to the driven members, but drives any driven members. Needless to say, it can be used for motor control.

[0069]

As is apparent from the above description, according to the present invention, in a motor control device for controlling the driving of a motor controlled by a combination of a plurality of phase signals, the speed of the motor is set stepwise. A speed table memory for storing speed data for performing the operation, a memory access control unit for sequentially reading the speed table data without the control of a CPU that controls the entire motor drive control, and a data value read from the speed table To time data, a phase signal generating section for generating a phase switching signal for operating the motor based on the output of the time converting means, and a predetermined number of time data outputs of the time converting means. Prompts the memory access control unit to generate access to the next memory table. Adopts a configuration in which the interval control means for controlling so as to operate said time conversion means using the same data values read from, C that controls the entire drive control of the motor by the memory access control unit
Since the speed table memory is accessed independently of the control of the PU, the load on the CPU can be reduced, and the data read from the speed table memory can be loaded into the time conversion means. Further, according to the interval control means, the occurrence of access to the next memory table is encouraged, so that the load on the CPU can be reduced and a plurality of acceleration / deceleration patterns can be generated from a single table. There is an excellent effect that the required memory capacity for the table memory can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a motor control block employing the present invention.

FIG. 2 is a block diagram showing an overall configuration of a conventional motor control system.

FIG. 3 is an explanatory diagram showing a driving principle of a motor according to the present invention.

FIG. 4 is an explanatory diagram showing an outline of a motor acceleration operation according to the present invention.

FIG. 5 is an explanatory diagram showing acceleration timing in the embodiment of the present invention.

FIG. 6 is a block diagram showing details of a phase signal generation block in the embodiment of the present invention.

FIG. 7 is a block diagram showing the overall configuration of the first embodiment of the present invention.

FIG. 8 is a block diagram showing an overall configuration of a second embodiment of the present invention.

9 is a block diagram showing acceleration characteristics of a motor obtained by performing control by an interval register using the speed table of FIG. 13 in the present invention.

FIG. 10 is an explanatory diagram showing the operation from start to stop of the motor in the present invention.

FIG. 11 is a diagram illustrating a start-up of a motor according to the present invention → medium speed → high speed →
It is an explanatory view showing an operation up to a stop.

FIG. 12 is a table showing an example of an acceleration table according to the embodiment of the present invention.

FIG. 13 is a table showing an example of an acceleration table according to the embodiment of the present invention.

[Explanation of symbols]

 1000 motor control block 1001 memory access control unit 1002 time conversion circuit 1003 phase signal generation unit 1004 bus arbitration circuit 1006 interval register 2008 interface circuit 8000 motor control unit 8004 to 8006 motor control block 8008 system bus 8000a dedicated bus 7001 CPU 7008 RAM 8003 RAM 7002 ROM 8002 ROM 1005 TCU

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 2C480 CA02 CB03 EA29 5H570 AA20 BB20 DD07 EE10 FF01 FF02 FF03 FF04 FF05 JJ03 JJ11 JJ12 JJ17 JJ18 KK06 KK10 5H572 AA20 BB10 DD08 FF01 FF18 JJ18 A0505

Claims (4)

[Claims] 1. A motor control device for performing drive control of a motor controlled by a combination of a plurality of phase signals, comprising: a speed table memory storing speed data for setting the speed of the motor in a stepwise manner; A memory access control unit that sequentially reads data of the speed table without the control of a CPU that controls the entire drive control; a time conversion unit that converts data values read from the speed table into time data; A phase signal generating unit for generating a phase switching signal for operating the motor based on the output of the memory access control unit; Prompts the occurrence of access, and then uses the same data value read from the speed table Motor control device is characterized by providing an interval control means for controlling so as to operate the converter. 2. The CPU according to claim 1, wherein the memory access control unit starts a memory access from an arbitrary address in the speed table memory, ends the memory access at an arbitrary address, and controls a series of operations after the memory access is completed.
2. The motor control device according to claim 1, wherein an interrupt is generated. 3. The motor control device according to claim 1, wherein the memory access circuit has a bus arbitration unit for accessing a speed table memory for a plurality of motors to be drive-controlled. 4. A motor control signal according to claim 1, wherein said phase signal generator sequentially switches the contents of a register having a bit width capable of expressing a combination of phases for driving a motor and outputs the contents as a motor control signal. The motor control device according to any one of the preceding claims.