JPH0153812B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a programmable frequency generator for driving an inverter with an inductive load, such as a variable speed compressor motor for an air conditioner.

Conventional configurations and their problems Conventionally, in order to configure a programmable timer with a wide frequency division ratio, the frequency division ratio must be set over a wide range as shown in Figure 1, or a low bit programmable timer as shown in Figure 2 must be used. A method using a cascade connection of a counter and a binary counter is known. Incidentally, the frequency output divided by the programmable counter is expressed by the following equation.

_OUT = _OSC /n (n = 1 to (2 ^a - 1)) where _OSC is the reference oscillator input, _OUT is the frequency output, n is the frequency division ratio, and a is the number of address bits of the programmable counter.

FIG. 1 is an example in which the number of address bits a in the above formula is increased.

In the circuit shown in FIG. 1, a reference oscillation section 1 generates a frequency _OSC and inputs it to a programmable counter 2. On the other hand, output terminal ₀ of microcomputer 3
~ _(a-1) A binary address code is set in the address inputs P ₀ ~P _(a-1) of the programmable counter 2. _OUT is the output terminal that is the frequency-divided _OSC .

Here, if the number of address bits a is 8, the division ratio n will be 1 to 255, and the number of address bits a will be 8.
When is set to 10, the frequency division ratio n is 1 to 1023, and when the number of address bits a is 12, the frequency division ratio n is 1 to 4095, and in this way, the number of address bits a is
Although it is possible to achieve the desired purpose by selecting an appropriate number of counters, this structure is difficult because there are no multi-bit programmable counters on the market, and the number of address outputs from the microcomputer increases, making the software complicated. It has the following disadvantages.

Next, the structure shown in FIG. 2 will be explained.

In the figure, 1, 2, and 3 are the same reference oscillation section, programmable counter, and microcomputer as in FIG. 1, and 4 is a several-stage binary counter section. The output _OUT of this circuit is the output of each stage of the binary counter section 4, which is sent to the microcomputer 3.
The output selection unit 5 selects and outputs the signals using the output terminals ₀₁ to _0x .

As an example, if programmable counter 2 is 8 bits and _OSC /600 is required as output _OUT , the frequency division range of programmable counter 2 is such that the division ratio n is 1.
~255, so its output is _OUT = _OSC / (150×
2 ² ).

Therefore, the address code output from the output terminals _O7 ~ ₀ of the microcomputer 3 is
10010110, which can be obtained by setting only the output terminal _{0 (x-2)} of the microcomputer 3 to "H". Although this method has the advantage of allowing the frequency division ratio to be created arbitrarily to some extent and can be configured using general-purpose ICs on the market, it requires a large number of parts and occupies many output terminals of the microcomputer, making it impractical.

Purpose of the Invention In order to overcome the above conventional drawbacks, the present invention provides a programmable counter that uses a general-purpose IC, does not place a large burden on the software of a microcomputer, does not occupy many output terminals, and has a simple circuit configuration. The purpose is to obtain the following.

Composition of the Invention The present invention synthesizes frequencies in a range that can be tracked sufficiently by a microcomputer by frequency division using software of the microcomputer, and directly outputs the output of a programmable counter in a frequency range above that frequency. This is a system that equivalently configures a cascade circuit of a binary counter and a binary counter to synthesize the frequency applied to an inverter with an inductive load. It has a high degree of freedom.

DESCRIPTION OF EMBODIMENTS Hereinafter, as an embodiment of the present invention, the configuration of a PWM type original oscillation circuit for a room air conditioner inverter will be described with reference to FIG. The PWM method is an abbreviation for pulse width modulation method, and is a method in which a voltage chopping algorithm is configured so that the integral value over time of the voltage applied to the inverter approximates a sine wave.

In the figure, 1 is a reference frequency generator that generates a reference frequency _OSC , 2 is a general-purpose programmable counter with a built-in binary counter, and 3 is a P-
MOS microcomputer, 4 is a binary counter built into programmable counter 2,
5 is data ₁ , ₂ and
This is a selective output circuit that selects and outputs ₃ .

In the above configuration, the frequency _OSC generated by the reference frequency oscillator 1 is transmitted to the programmable counter 2.
CLK is input to the terminal, address input P ₀ ~ P ₇
The address code is input from outputs ₀ to ₇ of the microcomputer 3, and the frequency division ratio is determined. The direct output of programmable counter 2 is ₁ ,
The output of the binary counter 4 built into the programmable counter 2 is ₂ , and this output ₂ is input to the interrupt input _I0 of the microcomputer 3. The output ₂ is frequency-divided by the software of the microcomputer ₃ and the final frequency output _OUT is selectively outputted via the selection output circuit 5 designated by the output terminals ₀₁ to ₀₃ of the microcomputer 3 depending on the frequency range. . Here ₁ =
_OSC /n (n=1-255), ₂ = _OSC /(2×n)
(n=1~255), ₃ = _OSC (2×n×m)(n=1
~
255, m=1, 2, 3...). By the way, n
is a binary code added to the address input (P ₀ to _{P 7} ) of the programmable counter 2, and m is a frequency division ratio determined by the software of the microcomputer 3.

Here, the microcomputer 3 is usually in charge of controlling other systems, and the speed cannot be so high. Therefore, when the output ₃ is output, the output ₂ needs to be set to a relatively low frequency.

The PWM system for room air conditioner inverters usually uses the motor's synchronous frequency ₀ multiplied by a carrier as the primary oscillation, and the calculation results for one example are shown in Figure 4. The one shown in the figure has a carrier of 42, _{an OSC} of 320 KHz, and a frequency output range converted to a synchronous frequency so that it can be output in 1 Hz steps from 2 to 90 Hz. In the frequency division ratio column, the first term on the left, 85 to 254, is the programmable counter frequency division ratio, the second term, 2, is the output specification of the binary counter attached to the programmable counter, and the third term, the multiplier of 2, is the microcomputer software. It shows the frequency division ratio by wear.

Here, the normal use range for an air conditioner is 30 to 90Hz when converted to the motor's synchronous frequency. Frequencies below 15Hz are used only at startup, so while the motor is under normal rotational control, the microcomputer's address is All you need to do is to specify and specify the output of ₁ .

Furthermore, from Figure 4, when outputting ₃ , the maximum frequency input to the microcomputer _{is OSC} /
(2×136)≈1.1 KHz, and this value is a value that even a commercially available 4-bit microcomputer can follow and process. Furthermore, if the input _I0 of the microcomputer 3 cannot be used as an interrupt input, the output ₃ can be synthesized using a software timer. In this case as well, the burden on the software is small because it is only at the time of starting.

Effects of the Invention According to the present invention, when a programmable frequency generator generates an arbitrary frequency, a relatively low frequency part is handled by frequency division by a microcomputer, so that the system can be easily realized without increasing the number of components. The frequency division ratio can be changed freely, and the software only requires frequency division processing when starting the motor, which reduces the burden on the user.As a result, the basic programmable counter can be configured with a general-purpose, inexpensive counter. There are great advantages in terms of cost, and since the frequency division ratio by software can be reduced to a fraction of an integer, there is a greater degree of freedom in changing the frequency division ratio compared to the conventional configuration of programmable counters and binary counters. Furthermore, as for the burden on the software, when using interrupt input, it is only a matter of specifying the frequency division and selecting the output, so it is much simpler than using a multi-bit programmable counter.
It has various advantages.

[Brief explanation of drawings]

1 and 2 are circuit diagrams of a programmable timer showing different conventional examples, FIG. 3 is a circuit diagram of a programmable frequency generator showing an embodiment of the present invention, and FIG. 4 is a circuit diagram of a programmable frequency generator showing an embodiment of the present invention. FIG. 2 is an explanatory diagram showing a specific design example. 1...Reference frequency generator, 2...Programmable counter, 3...Microcomputer, 4...
...Binary counter, 5...Selection output circuit.

Claims (1)

[Claims] 1 Consisting of a programmable counter equipped with an address input and a microcomputer equipped with a selection output, the address input of the programmable counter is operated by the microcomputer, and the output of the programmable counter is taken into an input terminal of the microcomputer, By setting a fixed frequency as a branching frequency, setting a frequency above the branching frequency as a regularly used range, setting a range below the branching frequency as a starting range, and switching the selection output of the microcomputer, the programmable frequency is set in the regularly used range. A programmable frequency generator for driving an inverter having an inductive load, which outputs the output of the counter as it is, and in the starting region includes a frequency-divided output of the output of the programmable counter by software of the microcomputer.