JPH0153810B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a programmable frequency generator that can be mainly applied to variable speed compressor motors for air conditioners, and can also be used for melody synthesis.

Conventional configurations and their problems Conventionally, in order to configure a programmable timer with a wide frequency division ratio, the frequency division ratio must be set over a wide range as shown in Figure 1, or a low bit programmable timer as shown in Figure 2 must be used. A method using a cascade connection of a counter and a binary counter is known. Incidentally, the frequency output divided by the programmable counter is expressed by the following equation.

_OUT = _OSC /n (n = 1 to (2 ^a - 1)) where _OSC is the reference oscillator input, _OUT is the frequency output, n is the frequency division ratio, and a is the number of address bits of the programmable counter.

FIG. 1 is an example in which the number a of address bits in the above formula is increased.

In the circuit shown in FIG. 1, a reference oscillation section 1 generates a frequency _OSC and inputs it to a programmable counter 2. On the other hand, output terminal ₀ of microcomputer 3
From ~ _(a-1) , a binary address code is set in the address inputs P ₀ ~P _(a-1) of the programmable counter 2. _OUT is the output terminal that is the frequency-divided _OSC .

Here, if the number of address bits a is 8, the division ratio n will be 1 to 255, and the number of address bits a will be 8.
When is set to 10, the frequency division ratio n is 1 to 1023, and when the number of address bits a is 12, the frequency division ratio n is 1 to 4095, and in this way, the number of address bits a is
Although it is possible to achieve the desired purpose by selecting an appropriate number of counters, this structure is difficult because there are no multi-bit programmable counters on the market, and the number of address outputs from the microcomputer increases, making the software complicated. It has the following disadvantages.

Next, the structure shown in FIG. 2 will be explained.

In the figure, 1, 2, and 3 are the same reference oscillation section, programmable counter, and microcomputer as in FIG. 1, and 4 is a several-stage binary counter section. The output _OUT of this circuit is the output of each stage of the binary counter section 4, which is sent to the microcomputer 3.
Output selection unit 5 that selects using outputs ₀₁ to _0x
Selected output is made by

As an example, if programmable counter 2 is 8 bits and _OSC /600 is required as output _OUT , the frequency division range of programmable counter 2 is such that the division ratio n is 1.
~255, so its output is _OUT = _OSC / (150×
2 ² ).

Therefore, the address code output from output terminals ₇ to ₀ of microcomputer 3 is
10010110, which can be obtained by setting only the output terminal _{0 (x-2)} of the microcomputer 3 to "H". Although this method has the advantage of allowing the frequency division ratio to be created arbitrarily to some extent and can be configured using general-purpose ICs on the market, it requires a large number of parts and occupies many output terminals of the microcomputer, making it impractical.

Purpose of the Invention In order to overcome the above conventional drawbacks, the present invention provides a programmable counter that uses a general-purpose IC, does not place a large burden on the software of a microcomputer, does not occupy many output terminals, and has a simple circuit configuration. The purpose is to obtain the following.

Composition of the Invention The present invention synthesizes frequencies in a range that can be tracked sufficiently by a microcomputer by frequency division using software of the microcomputer, and directly outputs the output of a programmable counter in a frequency range above that frequency. A cascade circuit of a binary counter and a binary counter is equivalently constructed, and the software frequency division is set to an arbitrary integer, giving a higher degree of freedom than using a binary counter.

DESCRIPTION OF EMBODIMENTS Hereinafter, as an embodiment of the present invention, the configuration of a PWM type original oscillation circuit for a room air conditioner inverter will be described with reference to FIG. The PWM method is an abbreviation for pulse width modulation method, and is a method in which a voltage chopping algorithm is configured so that the integral value over time of the voltage applied to the inverter approximates a sine wave.

In the figure, 1 is a reference frequency generator that generates a reference frequency _OSC , 2 is a general-purpose programmable counter with a built-in binary counter, and 3 is a P-
MOS microcomputer, 4 is a binary counter built into programmable counter 2,
5 is data ₁ , ₂ and
This is a selective output circuit that selects and outputs ₃ .

In the above configuration, the frequency _OSC generated by the reference frequency generator 1 is controlled by the programmable counter 2.
The address code is input to the CLK terminal of the microcomputer 3 from the outputs ₀ to ₇ of the microcomputer 3 to the address inputs P ₀ to _{P 7} to determine the frequency division ratio. The direct output of the programmable counter 2 is ₁ , and the output of the binary counter 4 built into the programmable counter 2 is ₂ , and this output ₂ is input to the interrupt input _I0 of the microcomputer 3. The output ₂ is frequency-divided by the software of the microcomputer ₃ and the final frequency output _OUT is selectively outputted via the selection output circuit 5 designated by the output terminals ₀₁ to ₀₃ of the microcomputer 3 depending on the frequency range. . Here ₁ =
_OSC /n (n=1-255), ₂ = _OSC /(2×n)
(n=1~255), ₃ = _OSC /(2×n×m)(n=
1 to 255, m=1, 2, 3...). Incidentally, n is a binary code added to the address input (P ₀ to P ₇ ) of the programmable counter 2, and m is a frequency division ratio determined by the software of the microcomputer 3.

Here, the microcomputer 3 is usually in charge of controlling other systems, and the speed cannot be so high. Therefore, when the output ₃ is output, the output ₂ needs to be set to a relatively low frequency.

The PWM system for room air conditioner inverters usually uses the motor's synchronous frequency ₀ multiplied by a carrier as the primary oscillation, and the calculation results for one example are shown in Figure 4. The one shown in the same figure has a carrier of 42, _{an OSC} of 320 KHz, and a frequency output range converted to a synchronous frequency that can be output in 1 Hz steps from 2 to 90 Hz. In the frequency division ratio column, the first term on the left, 85 to 254, is the programmable counter frequency division ratio, and the second term is the output specification of the binary counter attached to the programmable counter.
The multiplier of 2 in the third term indicates the frequency division ratio determined by the software of the microcomputer.

From Figure 4, when outputting ₃ , the maximum frequency input to the microcomputer is _OSC / (2 ×
136) is about 1.1 KHz, which is a value that even a commercially available 4-bit microcomputer can follow and process. Furthermore, if the input _I0 of the microcomputer 3 cannot be used as an interrupt input, the output ₃ can be synthesized using a software timer.

In this embodiment, the PWM method of an inverter for a room air conditioner has been described, but it can be similarly implemented for applications requiring a wide dynamic range of frequencies, such as melody synthesis.

Effects of the Invention According to the present invention, when a programmable frequency generator generates an arbitrary frequency, a relatively low frequency part is handled by frequency division by a microcomputer, so that the system can be easily realized without increasing the number of components. The frequency division ratio can be freely changed, and as a result, the basic programmable counter can be configured with general-purpose, inexpensive counters, resulting in a great cost advantage. 1, the degree of freedom in the frequency division ratio is higher than in the conventional configuration of a programmable counter and a binary counter.Furthermore, as for the burden on the software, when using interrupt input, it is simply a matter of specifying the frequency division and Since it only requires output selection, it has various advantages such as being simpler than using a multi-bit programmable counter.

[Brief explanation of drawings]

1 and 2 are circuit diagrams of a programmable timer showing different conventional examples, FIG. 3 is a circuit diagram of a programmable frequency generator showing an embodiment of the present invention, and FIG. 4 is a circuit diagram of a programmable frequency generator showing an embodiment of the present invention. FIG. 2 is an explanatory diagram showing a specific design example. 1...Reference frequency generator, 2...Programmable counter, 3...Microcomputer, 4...
...Binary counter, 5...Selection output circuit.

Claims (1)

[Claims] 1 Consisting of a programmable counter equipped with an address input and a microcomputer equipped with a selection output, the address input of the programmable counter is operated by the microcomputer, and the output of the programmable counter is taken into an input terminal of the microcomputer, By setting a fixed frequency as the branching frequency and switching the selection output of the microcomputer, the output of the programmable counter is output as is in the frequency range above the branching frequency and up to the upper limit frequency, and in the frequency range below the branching frequency and up to the upper limit frequency. A programmable frequency generator in which the output of the programmable counter is divided by software of the microcomputer in a frequency range up to a lower limit frequency.