JPS59169368A - Controller for inverter - Google Patents

Abstract

PURPOSE:To obtain a plurality of frequency specifications by an inverter by producing a plurality of types of frequency division clock signals by dividing the frequency of a clock signal from an oscillator, selecting it to read out it from a memory cell and altering the frequency. CONSTITUTION:The output of a frequency setter 4 is applied to a rate multiplier 6 and an ROM 8, the clock signal from an oscillator 12 is counted by a 4-bit binary counter 13 of a frequency divider, and added through a data selector 14 to the multiplier 6. The stored content of the ROM 8 is read out by a binary counter 7, and a signal matched to the output of the setter 4 is obtained from a data selector 10, thereby controlling transistors Tr1-Tr6 of 3-phase bridge inverter 1. Accordingly, when a main component section 24 is integrated, the oscillator 12 may not be altered, and a plurality of frequency specifications can be obtained by an inverter.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an inverter that obtains variable voltage and variable frequency output, and particularly relates to an inverter control device that is effective when the circuit of the control section is made into a prefectural circuit.

[Technical background of the invention]

For example, when controlling the rotational speed of an AC motor to perform constant torque operation, a variable voltage, variable frequency power source is used to control the motor speed while keeping the ratio of motor terminal voltage and frequency constant. things will be done. In this case, an inverter is the most common variable voltage, variable frequency power source.

FIG. 1 shows the configuration of a typical six-phase bridge inverter main circuit 1. As shown in FIG. In this case, transistors are used as switching elements, and each arm of the three-phase bridge is connected to a transistor 'prl.

Tr2. Try, Tr4. Try, Tr6, each collector Q of these transistors Tri to Tr6
A flywheel diode D is connected between each emitter. Then, transistors Tr+ and Tv4. TV
2 and Tv5. Each interconnection point of Tv3 and Tv6 is connected to an output terminal T U and T v, respectively.

Tw, and these output terminals TU, Tv,
A six-phase AC motor as a load is connected to the TW.

Furthermore, power is supplied to the inverter main circuit 1 having this configuration from the DC power source 2, and the transistors Tri to Tv6 are operated using a pulse width modulation method (hereinafter simply referred to as the P Vv' M method).
By adopting and switching the output terminal TU
, Tv, and Tw, the frequency of which can be adjusted by changing the switching period of each transistor Trl to Tv6. still,
6 is a capacitor for smoothing the direct current component.

FIG. 2 shows a conventional inverter control circuit.

To simplify the explanation, only one phase will be described.
In the figure, reference numeral 4 denotes a frequency setting circuit that outputs a frequency setting signal S1 for setting the output frequency f of the inverter king circuit 1. ) 8 is tied to 4. Reference numeral 5 denotes an oscillator for generating a clock signal S2 that determines the output frequency f.

The rate multiplier 6 is used to control the output voltage of the inverter main circuit 1 so that it has a predetermined ratio relationship with the set frequency if, and controls the frequency of the clock signal S2 at a division ratio according to the frequency setting signal Sl. A new lock signal S2a is output by changing the lock signal S2a.

7 counts the clock signal S2a outputted from the rate multiplier 6; it is a binary counter for forming the JV extraction circuit. The ROM 8 receives the output from the binary counter 7 and the frequency setting signal SI from the frequency setting circuit 4.
8 stores a predetermined logic pattern for obtaining heavy pressure corresponding to the set frequencies f1 to fn of the inverter main circuit 1, and in this example, every 60 minutes is stored for 180 minutes, and the binary counter 7 is stored in the ROM with 30 minutes as one cycle. F3
Read out the memory contents of and set electrical angles of 0° to 30°, 30° to 60°, and 60° to 90° to the output terminals DO to D5, respectively.
°, 90°~120°, 120°~150°, 1
A data signal S4 of 500 to 180 minutes is output. 9
6 receives the carry signal S8 from the binary counter 7
This counter is used to output a select signal S5 for causing the data selector 10 for the storage element to select the data signal S4 from the ROM'13. In this way, the output of the data selector 10 is 0 in electrical angle.
A signal S6 of up to 180 minutes is output from the frequency setting circuit 4, that is, at a frequency commensurate with the set speed. Reference numeral 11 indicates an inverting port 1, from which a signal S7 conjugate with the signal S6 is obtained, and a signal S7 is obtained that is conjugate with the signal S6.
For HTr4, it is given as S7, while S6. Each of S7 becomes a signal with an electrical angle of 180 to 660 for Tv4 and Trz, respectively.

[Problems with background technology]

In the case of such a circuit configuration, conventionally, a fixed frequency oscillator such as a crystal oscillator or a ceramic oscillator is used as the oscillator 5.
To obtain frequency steps of 12H2 and 2Hz pitch, if the number of words of the 300-minute data signal S4 is 256, then 256X12X 255/X512=15667
A generator with an oscillation frequency of 20 (Hz)56 is required.

Here, due to the miniaturization of equipment and economic demands, for example, the second
When integrating the control section within the two-dot chain line in the figure, the maximum frequency and frequency pitch of the oscillator 5 will be uniquely determined if the circuit configuration is used as is. For example, when multiple frequency specifications are required for one inverter device, it is necessary to change the external oscillator 5 itself.

On the other hand, the data for 30° stored in the ROM13 is a pulse train MO obtained by comparing the sine wave Sa and the triangular wave sb, as shown in FIG. ) is quantized and applied. For this reason, for example, when changing the number of words by half due to cost considerations, if the excavator 5 was used as is, the output frequency would double.
Therefore, in this case, countermeasures such as changing the frequency of the oscillator of the oscillator 5 are required, which leads to the disadvantage that standardization of basic circuit parts becomes uneconomical.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and its purpose is to provide an inverter control device that achieves effects such as being able to obtain a frequency specification of 4>1 d without adding any changes to the oscillator. There is K.

[Summary of the invention]

The inverter control device of the present invention maintains a predetermined ratio relationship between frequency and voltage by controlling the switching elements of the inverter main circuit on and off using data stored in storage elements in voltage patterns corresponding to each set frequency. In an inverter configured to obtain variable frequency and variable voltage compression, a frequency dividing circuit is provided that divides the clock signal from the generator and outputs a plurality of types of frequency-divided clock signals, and the frequency-divided clock signal is By making a selection, the read frequency of the voltage pattern from the memory element can be changed.

[Embodiments of the invention]

Next, an embodiment of the present invention will be described with reference to FIGS. 1, 4, and 5. Here, only one phase will be described to simplify the explanation.

In FIG. 4, the circuit configuration is similar to the conventional example, but in this example, the clock signal S8 from the oscillator 12 is provided to be counted by a 4-bit binary counter 13, which is a frequency dividing circuit. , this binary counter 1
The clock signal S8 is divided by 2, 4, 8, and 16 from the output terminal Q'+Q, ]+Q 2 'l Q '' of 3.
S12 is output respectively. Further, 14 indicates frequency-divided clock signals S 9 and S 1o.

Sl 1. This is a data selector for the frequency divider circuit that receives Sl2, and its specific configuration is as shown in FIG. That is, the frequency dividing circuit data selector 14
D game) 15, 16, 17-18° 19 and inverters 20, 21 are connected as shown. Therefore, input to the select terminals 22 and 23 respectively n
The instruction signals St8 and Sl4 have logical values JO and DJ, respectively.
In this case, only the NAND gate 15 is open and the branch clock signal S9 from the binary counter 16 is N.A.
It is output from the ND gate 19 as a signal for determining the output frequency. Similarly, when the instruction signals S1B and S14 have the logical value "1" and Oj, the divided clock signal S+o is outputted from the NAND gate 19 via the NAND gate 16, and the instruction signals S]8 and S14 have the logical value "1" and "Oj", respectively. i-0,f
In the case of J (in the case of N A N D gate 17
A hy D gate 19 to divided clock lli S
I1 is output, and the instruction signal S+a.

S14 is a logical value J1. In the case of IJ, the frequency-divided clock signal SI2 is output from the NAND gate 19 via the NAND gate 18. The components described above are different from the conventional ones, and there are 5 other frequency setting circuits 4.
Rate multiplier 6, binary counter 7, ROM
8. Hexadecimal counter 9. Memory element data selector 101
The inversion circuit 11 has the same configuration as the conventional one.

The operation of the circuit shown in FIG. 4 constructed as above will be explained. That is, the clock signal S8 output from the oscillator 12
are divided by 2, 4, 8, and 16 by the binary counter 13iC, respectively, and each divided clock signal S9.n1 is divided in this manner. SlO, Sll, and S12 are input to the frequency divider circuit data selector 14. In this case, for example, the logic value "1.0" is set for each of the select terminals 22 and 26.
” instruction signal S+8. When SI4 is input, a frequency-divided clock signal 510 (ie, a signal obtained by dividing the clock signal S8 by four) is outputted from the frequency-dividing circuit data selector 14 and inputted to the rate multiplier 6. On the other hand, the frequency setting signal Sl from the frequency setting circuit 4 is given to the rate multiplier 6 and the ROM 8. The rate multiplier 6 outputs the output voltage V of the impark main circuit 1.
The frequency of the frequency-divided clock signal S10 is changed at a frequency division ratio according to the frequency setting signal Sl so that the frequency has a predetermined ratio relationship with the set frequency f, and a new limp lock signal 5tOa is output. The above clock signal S>oa is the binary counter 7
The binary counter 7 outputs a binary signal. Each address of ROki 8 is repeatedly addressed by the binary signal output in this way, and the ROM
8 output terminals DO~D5/ respectively from electrical angle 00~300.30°~6 [10,6
0°-90°, 90°-120°? 1200-150
A data signal S4 of +1500 to +1800 minutes is output. On the other hand, the carry signal S8 from the most significant digit of the binary counter 7 is input to the hexadecimal counter 9, and the select signal S5 output from the hexadecimal counter 9 according to
This causes the storage element data selector 10 to select and pass the data signal S4 from the ROM 8. In this way, the signal S6 for 0 to 180 degrees in electrical angle is output from the memory element data selector 10 to the frequency setting signal S+.
(ie, the set speed). Then, in the inverting circuit 11, a signal S conjugate to the signal S6 is
7 is obtained, and these signals S6 and S7 cause the transistor Tr1°Tr in the inverter main circuit 1 shown in FIG.
4 is driven.

As described above, the instruction signal S18. S14 each have a logical value "1"
．． In the DJ state, the oscillation frequency of the oscillator 12 is, for example, 1.
If it is 566720Hz, ・Inverter main circuit 1
The maximum frequency fmax obtained by n is: fmax = 1566720X 256/255 I1
2×2'56×+=128Hz, and the frequency pitch is 0.5H2.

In addition, the instruction signals S+a and S+4 are husband; r "0, 0"
In the state (that is, the state in which the frequency-divided clock signal S9 obtained by dividing the clock signal S8 by two is given to the rate multiplier 6), the maximum frequency fmax obtained by the inverter main circuit 1 is 256H2, and the frequency pitch is IHz. .

Similarly, the instruction signals S18 and SI4 are respectively J0. The state of IJ (that is, the state in which the clock signal S8 is divided by 8 and the large frequency divided clock signal S11 is sent to the rate multiplier B by 4)
In this case, the maximum frequency fmax is 64 Hz, the frequency pitch is 0.25 Hz, and the instruction signals Sts and S14 are in the state of r1' and IJ, respectively (that is, the divided clock signal S12, which is the clock signal divided by 16, is the rate multiplier). In the situation given to Party B), the maximum frequency fmax is 32Hz
, the frequency pitch becomes o125H2.

According to the above configuration, when the control section 24 in the converter, for example, shown by the two-dot chain line in FIG. The quality of the characteristics of a motor operated by one inverter is often determined uniquely, and four types of maximum frequencies and two frequency pitches can be obtained.

It is economically advantageous to be able to select the maximum frequency that matches the quality of rotation.

In the embodiment, a three-phase case has been described, but it goes without saying that a single-phase case can also be realized by using the signals for one phase.

In addition, the frequency division ratio by the binary counter 13 may be changed, or the number of types of branch clock signals may be further increased.
The number of inputs to the frequency dividing circuit data selector 14 may be increased accordingly.

〔Effect of the invention〕

As explained above, the present invention provides a frequency divider circuit that divides the frequency of a clock signal from an oscillator and outputs a plurality of types of frequency-divided clock signals, and selects the frequency-divided clock signal to generate a voltage pattern from a storage element. Since the readout frequency of the oscillator can be changed, when the main components are integrated into an integrated circuit, multiple frequency specifications can be obtained with one inverter device without changing the oscillator, resulting in a balance between cost and performance. It is possible to realize an inverter control device with a high degree of accuracy.

[Brief explanation of drawings]

Fig. 1 is a wiring diagram showing the conventional inverter main circuit configuration, Fig. 2 is a block diagram showing the control circuit of the conventional inverter main circuit, Fig. 3 is a diagram showing a method for determining the contents to be stored in ROM, FIG. 4 is a block diagram showing an embodiment of the present invention, and FIG. 5 is a tax chart of the main parts. In the figure, 4 is a frequency setting circuit, 6 is a rate multiplier, 7 is a binary counter, 8 is a ROM (memory element), 9
is a hexadecimal counter, 10 is a data selector for storage element, 1
2 is an oscillator, 16 is a binary counter (branch circuit), 1
4 is a data selector for the frequency dividing circuit. Applicant: Tokyo Shibaura Electric Co., Ltd. ~1

Claims (1)

[Claims] 1. A frequency dividing circuit that generates a clock signal with a constant period, a frequency dividing circuit that divides the frequency of the clock signal and outputs multiple types of branch clock signals as signals for frequency determination, and a frequency dividing circuit that divides the frequency of the frequency-divided clock signal. A rate multiplier that is provided to be selectively inputted via a frequency circuit data selector and divides the n-core frequency division clock signal by a division ratio according to a frequency setting signal to change its frequency. a memory element in which the on/off timing of the switching elements of the inverter is recorded in order to obtain a voltage pattern corresponding to the frequency fine setting value; An inverter control device comprising: a binary counter for addressing, a counter for counting the output of the binary counter, and a data selector for storage elements that uses the outputs of the above elements as data and the output of the counter as a select signal.