JPS59201683A - Control circuit of inverter - Google Patents

Abstract

PURPOSE:To improve the resolution in an ROM of the same capacity and to improve the control efficiency by storing 6 types of signal patterns to an AC control signal one period, and constructing to enable to simultaneously output the signal patterns. CONSTITUTION:An AC control signal one perid is divided into six and data corresponding to the electric angles are stored to be outputted to 1-bit-6-bit on an ROM6. The outputted signals are inputted to a data selector 8. The data is selected upon receiving of a signal of a sexanary ring counter 7 which operates with the 8th bit frequency of a counter 5 as a clock, an AC control signal one period is formed, and delayed at every 120 deg., and other 2-phase AC control signals are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inverter control circuit that uses a memory element to control an inverter according to an energization pattern stored in the memory element.

FIG. 1 shows an example of a conventional circuit. In the figure, (1) is a frequency data generator that generates a 12-bit output; (2) is a frequency data generator that generates a 12-bit output;
) 汀V-) Multiplier, (3) is a generator, (4)
fd frequency divider, (5) ha counter, and (6) held-on memory (hereinafter referred to as ROM). Of the 12 bits output from frequency data generator B (1), 4 bits are stored in the ROM (
6), the remaining 8 bits are the rate multiplier (2)
It is connected to the. The output signal Fo of the rate multiplier (2) is given by FO-'2·Fi-56. Here, K (d is a constant determined by the 8-bit input, Fi is the oscillation frequency output from the oscillator (3). The output signal FO14 is divided by the frequency divider (4) to the frequency Fcr as described later, and the counter (5) is input.R
Considering that OM (6) has a storage capacity of 4096 words and 8 bits, the output of counter (5) can be 8 bits.

Frequency F8 of 8th bit, 7th bit of counter (5) U formula 1
7) Also, Figure #j2 shows the basic circuit of a generally used transistor type three-phase inverter. If the frequency F8 is selected to match one cycle of the AC control signal given to the circuit shown in Fig. 2, the ROM (6) [3 as shown in Fig. 3]
All data for A'D can be stored. As a result, the 4-bit signal from the frequency data generator (1) is used to store 256 categories of AC side power signals, which are 16 types of data. Therefore, there is a drawback that the resolution of one data is extremely low and V'C is very low.

This invention is an impark control circuit made to eliminate the above-mentioned drawbacks, in which the 1st sign controlling the AC is a repetition of the same data with a deviation of about 120 degrees a.VC7￥ The aim is to minimize the amount of storage in the ROM and improve the resolution of the ROM's father flow control (J).

Hereinafter, one embodiment of the present invention will be illustrated in Figure 11. I will clarify. In the 4th M, (1) to (6) are the same as shown in FIG. 1, (7) is a hexadecimal ring counter, and (8) is a Hadague selector. RO! A (+3) has the 5th I Nu 1
As shown in (C-cross side power signal - the period is divided into 6 parts, and the data corresponding to each 'rff air angle' is stored in such a way that it is output from 1 to 6 bits). The 1st signal is outputted to the data selector (8), inputted to the counter (
5) The frequency of the 8th bit is 1, and the clock is 8.
The hexadecimal ring counter (7) that generates selects data using the signal gate, and the AC side forms one cycle of the 1x signal, and further,
AC control signals for the two phases of the pond are formed by delaying them by 120°.

Therefore, according to this embodiment circuit, if the frequency of the 8th bit of the counter (5) is selected to be equal to the number of circumferences of 7 m corresponding to 6 electrical angles of the AC control signal, Since the data corresponding to an angle of 60° is stored over 256 sections, the resolution of one data is increased, resulting in a resolution six times higher than that of the conventional circuit.

As explained above, according to the present invention, ROMs of the same capacity
In this case, a resolution twice as high as that of the conventional method can be obtained for the AC control signal, making it possible to improve control efficiency.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the control path of a conventional inverter, and Fig. 2 is a basic circuit diagram of a transistor type three-phase inverter, fj3.
Section 1 is a diagram illustrating a storage method in a read-on memory of a conventional device, FIG. 4 is a control circuit diagram of an inverter showing an embodiment of this invention, and FIG. It is a figure explaining the storage method of. In the figure, (1) is a frequency data foil generator, (2) is a rate multiplier, (3) is an oscillator, (4'lig frequency divider,
(5) is a counter, (6) is a read-on memory, (7 is a
) 146-decimal ring counter, (8) is a data selector. Note that the same - symbol in +W indicates the same - or a corresponding part. Agent Masuo Oiwa

Claims (3)

[Claims] (1) 3, 1 of the inverter that obtains l'th AC power
The phase AC control signal is divided into electrical angle intervals of 60 degrees, six types of signal patterns are stored in one memory for one cycle of the AC control signal, and the above six types of signal patterns are stored from this storage device. An inverter control circuit characterized in that it is configured to enable simultaneous output. (2) The signal pattern of the six buildings shall be formed into a predetermined AC control signal by a data selector that operates based on a hexadecimal ring counter that operates at a black rate corresponding to electrical angle 6 (y'). An inverter control circuit according to claim 1, characterized in that: (3) It is characterized in that it is configured such that all six types of signal bagoons are inputted with a phase difference of 120', and all AC control signals for three phases are generated from the data in the lead-on memory for one phase. An inverter control circuit according to claim 1.