JPS58179382A - Informing sound generating circuit of timepiece - Google Patents

Abstract

PURPOSE:To generate an artificial sound of a voice of a bird, etc. by a comparatively simple circuit configuration, by dividing a voice of a bird, etc. into several frequencies and sound volumes, and generating plural artificial sounds by synthesizing an indicating signal of each frequency and an indicating signal of the sound volume. CONSTITUTION:A programable frequency divider 9 divides a clock signal phi1 in accordance with a frequency dividing ratio indicated by frequency indicating signals L5, L6 and outputs a frequency signal R. A sound volume varying circuit 10 varies a sound volume of the frequency signal R from the programable frequency divider 9 in accordance with sound volume indicating signals L0-L4 and L7, and outputs a signal V. This output signal from the sound volume varying circuit 10 is applied to a sound generator 11 and an informing sound is generated. Also, a curve X corresponding to ''cu'' of ''cuckoo'' is divided, for instance, into three frequencies f1, f2 and f3, is made an approximate sound whose sound volume is constant, and a curve Y corresponding to ''ckoo'' is converted to an approximate sound obtained by varying a sound volume only at constant frequency f4, and a data which combines data of such approximate sounds, namely, four frequency data, several sound volume data and one pause data, respectively is stored in an ROM 6.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock alarm sound generation circuit that generates a simulated sound such as a bird's voice using a relatively simple circuit configuration.

Conventionally, clocks, such as cuckoo clocks, have been proposed that emit a signal that simulates the sound of a bird's voice as a notification sound.
Many conventional watches of this type use mechanical sound-generating mechanisms such as bellows, because the simulated sound produced is close to the real thing.

However, the mechanical sound generating mechanism has a complicated structure, which increases the size of the watch and also causes an increase in cost.

Furthermore, such a sound generating mechanism has the disadvantage that it is extremely difficult to manufacture and install, and is prone to failure due to its complicated structure.

In recent years, electronic clocks have developed rapidly, and along with this, notification sounds have also become electronic.1. It has been proposed to digitize the pre-simulation of natural sounds such as the voice of - and use this as a notification sound.

In order to convert bird voices and the like into electronic sounds in this way, a method has been considered in which waveforms of bird voices and the like are stored in advance in a ROM serving as a storage means, and the waveforms are sequentially read out.

However, it is difficult to store in ROM K all the waveforms that show extremely complex changes, such as the frequency of a bird's voice, where the frequency rapidly changes continuously at short intervals, or irregularly intermittent. This results in drawbacks such as increased chromatography, increased prices, and difficulty in determining waveforms.

The present invention solves the drawbacks of the above-mentioned conventional example by dividing a bird's voice, etc. into several frequencies and volumes, and by synthesizing an instruction signal for each frequency and an instruction signal for the volume, a plurality of pseudo signals are generated. The purpose of this invention is to solve this problem and generate a pseudo sound such as a bird's voice using a relatively simple circuit configuration.

The following is a detailed explanation of the present invention based on the drawings.
The figure is a block circuit diagram showing one embodiment of the present invention.
Reference numeral 1 denotes a reference signal generation circuit, which generates a 32718 Hz clock signal pi using a crystal oscillator in this embodiment.
It is outputting s.

2 is a frequency dividing circuit which divides the frequency of the clock signal as appropriate and outputs a clock signal 12*j'3 m 164 e^.

Clock signals ^, III, , llI4 in this embodiment
゜True and 1024 Hz and 128 Hz respectively
, 32 Hz, and 4 Hz.

Reference numeral 3 denotes a clock drive circuit, which inputs the clock signal output from the frequency dividing circuit 2 to drive the clock.

Reference numeral 4 denotes a frequency/volume instruction signal output circuit composed of an address counter 5 and a ROM 6.

The address counter 5 inputs and counts the clock signal true from the frequency dividing circuit 2, and outputs 9 R from Hb to H6.
Specify an address in OM b and output the data stored at each address. - The address counter 5 starts counting υ by inputting the start signal A2 from the start signal generating circuit means 7, which is constituted by an alarm circuit 8' and a repetition counter 8. , it stops when it finishes counting.

Thereafter, when a predetermined time has elapsed, the repetition counter 8 outputs a repetition signal D! is output, and the address counter 5 which receives this signal starts counting again.

The ROM 6 that stores the frequency and volume of the notification sound is
Each time the address counter 5 starts counting due to the repeated signal, the data stored at the address specified by the address counter 5 is outputted.

In addition, the signal output from the address counter 5 has RO
This is the rounding signal that activates M-6.

Among the output signals L0 to L7 output from ROM b,
Frequency instruction signals Ls and L are clock signals! 11 is applied to the programmable frequency divider 9, which receives nine volume instruction signals L0 to L4. L7 is applied to the volume variable circuit 10.

The programmable frequency divider 9 receives a frequency instruction signal.

The clock signal s is specified by L and K according to the divide-by-nine ratio.
1 and outputs a frequency signal R.

The volume variable circuit 10 changes the volume of the frequency signal R from the programmable frequency divider 9 into volume instruction signals L0 to L4L, K.
Therefore, the signal V is output.

The output signal V from this volume variable circuit 10 is transmitted to the sound generator 1
1 and a notification sound is emitted.

The nine data stored in the ROM 6 in this embodiment are, for example, when storing the bird's voice "kako", the sound "kako" is minutely time-divided and a set of volume and frequency at each division point is created. It is not a collection of data and stored.

As shown in FIG. 2, the curve X corresponding to the "force" in "brackets" is plotted, for example, at three frequencies '1. '! l 'sl
C-divided into a nearby position with a constant volume, and a "co"
Converting the curve Y to a near position that can be obtained by changing only the volume with a constant frequency f4, data at such a near position, that is, four frequency data, several volume data, and one Data that is a combination of each pause data is stored.

FIG. 3 is a detailed circuit diagram of the start signal generating circuit 7 shown in FIG. 1.

The switch S in the alarm circuit 8' is turned on at a preset time by the operation of a timekeeping mechanism, or is simply a manual switch or a time signal switch that is turned on at a fixed time.

When switch S is turned ON, signal A! is output from 7 lip 70 knob 12. is output.

This signal A is inverted to 1 by an inverter 16 and applied to the address color/receiver 5 as a start signal A2.
The tint gate 15, which receives the start signal A2 and the clock signal inverted by the inverter 14, outputs a good signal B in synchronization with the clock signals when the switch S is turned on.

This signal B is filtered by flip-flops 16, 17, and 18 which operate according to the falling edge of the input signal, and is applied to the AND gate 19 as an output signal C1.

The output signal C2 of the flip-flop 17 is applied to the other input terminal of the AND gate 19.
9, the signal C2 and the signal C1 are combined to form the signal D1 which is applied to the flip-flop 20.

The flip-flop 20 that receives the signal D1 outputs the signal at the falling edge of the clock signal 6, and via the OR gate 21, the flip-flop 1<S, 17.18
Set it. Through this operation, a trigger pulse signal D2 is obtained and sent to the address counter 5 via the inverter 22 as a repetitive signal.

FIG. 4 is a timing chart of the signals shown in FIG. When the switch S is turned on, the switching signal A1 changes from H level to L level. This signal A□ is passed through the 7-rip 70 tube 12 and the inverter 15 to become the signal A, and this signal is used as the start signal of the address counter 5.

The signal B is obtained by combining the signal 1, the clock signal ^, the &&L9 signal DA, and the Nant gate 15.

This signal B is sent in turn to the flip 70 tubes 16, 17, and 18.

The slip 70 knobs 16, 17, and 18 are reset via the shift flip knob 20 and the OR gate 21 by the AND gate 19 outputting a trigger pulse signal.

Therefore, the signal C2 is output from the AND gate 19, the flip 70 knob 17 is reset, and the trigger pulse 2 is generated during running.
It becomes 3.

★9. Output signal D1 of AND gate 19 is 7 rip 70
A good signal is sent from the knob 20K in synchronization with the falling edge of the clock signal Ii8, and a repeating signal that changes from the H level to the L level via the inverter 22 is sent.

becomes.

FIG. 5 is a detailed circuit diagram of address counter 5 shown in FIG. 1.

In FIG. 5, since the initial state of the start signal A from the repeat counter 8 is at the L level, the output of the Nant gate 24 of the address counter 5 is fixed at the H level.

That is, as shown in the timing chart of FIG. 6, the signal I is initially fixed at H level.

When the signal I is at H level, it is inverted by the inverter 25 and becomes the good signal Jt'iL level, and the Nant gate 26
The output of the counter 27 is fixed to prevent the clock signal true from being applied to the counter 27.

Further, the signal further inverted via the inverter 28 becomes the #'iH level, keeping the 7 lip-flops 29 to 36 in the reset state.

This signal is also applied to the ROM 6, and when the signal K is at H level, the ROM 6 is stopped.

When the start signal A becomes H level, the Nantes gate 2
All 40 inputs are at H level, and the outputs are at L level.

When the signalman goes to L level, signal J goes to H level,
Kutsk signal via Nantes gate 26 also 7 rip 7
The voltage is applied to the p-tub 29, and the counter 27 starts counting.

At this time, the signal K goes to the L level, so that the reset state of the clip 70 knobs 29 to 36 is released, and the ROM 6 becomes operable when the signal falls.

The counter 27 starts counting and the address signals H0-H
6 and the signal H7 becomes H level, the signal H7 becomes L level and the output of the Nant gate 24 becomes H level.

Due to this, the signal becomes 4H level and 7 rip 7
Reset c1 knobs 29 to 36 and stop ROM 6.

When the signal I goes to H level, all the input terminals of the Nant gate 370 go to H level, and the output goes to L level.
By resetting the counter 27, the signal ■7
becomes H level again, but at this time the output of Nantes gate 37 is fixed at L level, so Nantes gate 2
The output of No. 4 is fixed at H level. In this state, when the repeating signal goes to L level due to the trigger pulse, the output of Nandt gate 37 goes to H level and the output of Nandt gate 24 goes to L level.

The output of the Nandts gate 24 fixes the output of the Nandts gate 57 at the H level, and fixes the output of the Nandts gate 24 at the L level.

As a result of this operation, the counter 27 and the ROM 6 start operating again.

FIG. 7 is a diagram showing details of the input and output of the ROM 6 shown in FIG. 1.

The ROM 6 is activated when the signal from the address counter 5 falls.

The address counter 5 reaches the high level of the signal A2, and at the same time outputs the address signals H0 to H6.

ROM 6 Huff) 'L' signal The addresses indicated by signals -0 to H6 are read out and output signals L0 to L7 are output.

As mentioned above, the signals Ls, L are frequency instruction signals, and the signals L0 to L4 . L is a volume instruction signal.

The output signal of the ROM 6 differs depending on the stored content, but in this embodiment, it is stored to indicate the sound of a bird, ``kakko''.

The output of this ROM 6 is, for example, pre-stored data as shown in FIG.

In this example, the signals in the period 0 to 121 are the signals required for the "power" part of the bird's voice "kakko", and the signals in the period 13 to 421 are the signals required for the "tsu" part. There is a suspension period.

The output of the ":F-" portion is determined in the same manner.

FIG. 9 is a diagram showing a detailed circuit configuration of the programmable frequency divider 9 shown in FIG. 1.

The frequency instruction signal outputted from the ROM 6 is connected to one input terminal of the analogue game) 38 and 39, and to the inverter 42.
The voltage is applied to one input terminal of the analog gates 40 and 41 via the input terminals 40 and 41. Further, the frequency instruction signal L6 is applied to the other input terminals of the AND gates 38 and 40, and to the other input terminal of the AND gate 39.41 via the inverter 43.

The AND gates 38 to 41 synthesize the signals RI and IL and output the output signals M1 to M4.

These output signals M, -M4 are shown in the timing chart of FIG.

In Fig. 10, periods 0 to 12 are the period 0 to 12.
This is the period required for the ``power'' part of ``.

These signals M, -M4 are applied to the OR game) 44, 45, and are combined into the output signal N1-;N.

The signals N, , N2 and the signal M1 (,1) are applied to one input terminal of each of the AND gates 47°48.46, and the AND gates 46 Open and close ゜47.48.

Next, the operation of the programmable frequency divider circuit 9 shown in FIG. 9 will be explained using the timing charts shown in FIGS. 11 to 14.1 In FIG. 11, the signals M, , N, , N, respectively 10 is a diagram showing a timing chart of each signal in the case of L level, L level, and H level, that is, in the state of period 1 in FIG. 10. FIG.

The signal for operating the ROM 6 is applied to the R inputs of the 7-lip 70 tabs 51-58 of the programmable frequency divider circuit 9, and normally keeps the slip 70 tabs 51-58 in a reset state.

At the same time as this signal K goes to L level, flip-flops 51 to 58 are activated.
The signal being applied to the input4. is normally at H level, so when the reset is released, the Q output terminal is brought to L level in synchronization with the fall of clock signal j1. The flip-flop 57 normally receives an H level signal from the 4 output terminals of the 7-lip flop 56 to its D input, and when the reset is released, the clock M li1! 'bto' P9 and Mr. Yatoki (Matou Totame becomes L level.

At this time, the Q output of the flip-flop 56 becomes L level, and the Q output of the flip 70 knob 57 becomes H level in synchronization with the fall of the clock signal 1.

Output signal 01 from 7-rip-flop 56 and 7-rip 7
Noah game with output signal 0□W from 0tube 57)
59 and 60 synthesize the signals 01O8 to form the signal S,
This signal S is applied to the 7-rip 70 tube 58 and the OR gate 61, respectively.

The flip-flop 58 sets the Q output to H level in synchronization with the fall of the first pulse of the signal S.

The output signal S from the NOR gate 60 is combined with the clock signal p11 by the OR gate 61 to become a signal P, which is applied to the tritub flop 51, and the flip-flops 51 to
The frequency is divided by 55.

S input KH of flip-flop 53.54 via 49
The level is applied and 7 rip 70 lub 48.49 is set. Therefore, the output signal Q1. Q4 is signal Q
, does not reach H level before it falls, and as a result, the output signal Q of the flip-flop 55 is modulated.
Signal ζ, is o, I O! Since the period of the signal S is determined, the period of the signal S is essentially determined.

Since this signal S becomes the signal R via the tree flop 58, the signal R is modulated by the above-described operation.
One frequency of the signal R at this time is set to 780 Hz.

In FIG. 12, the signal M0 is at L level, the signal N1 is at H level,
10 is a timing chart of each signal in FIG. 9 when signal N is at H level.

As mentioned above, the signal S is a 7-lip 70-tub 56.5 whose reset state is released by the falling edge of the signal.
7 is generated by outputting the signal 01.0□. This signal S goes to H level and flip-flops 52, 53, and 54 are set. Therefore, these flip-flops 52, 53, and 54 make their outputs H level without synchronizing with the falling edge of the clock signal to which they are input.

Then, when the signal S goes to L level, the 7 lip-flop 5
The set state of 2.53.54 is released and the output is set to L in synchronization with the next falling edge of the input clock signal.
level.

In this way, the division ratios of flip-flops 51-55 are changed, the signal 4 output from flip-flop 55 is modulated, and therefore the signal 010. The synchronization of the good signal S will also change.

As a result, the frequency of the signal R output from the programmable frequency divider circuit 9 is changed.

In this embodiment, the signal M1 is at L level and the signal N1 is at H level.
The frequency of the signal N is set to 862 Hz when the signal N is at the H level.

FIG. 13 is a timing chart of each signal in FIG. 9 when the signal M1 is at H level, the signal N8 is at H level, and (FI 4 N2 is at H level).

When the signal M1 is at H level, the signal N1 is at H level, and the signal N2 is at H level, when the signal S goes to H level, the flip-flops 51 to 5 are connected via AND gates 46 to 49.
4 is set.

When the seven lip-flops 51 to 54 are set, their outputs go high without synchronizing with the input clock signal.

When the signal S falls and becomes L level, the flip 70
The tabs 51 to 54 set their outputs to L level in synchronization with the fall of the input clock signal. After that, the frequency of the j@th input signal is divided.

In this way, the division ratio is changed, 7 lip 70 lip 5
5 is modulated, and as a result, the period of the signal S also changes.

By changing the period of this signal S), Progera? The period of the output signal R of the frequency dividing circuit 9 is changed.

The frequency of signal R at this time is set to 910 HzK.

In FIG. 14, the signal MX is at L level, the signal N1 is at H level,
10 is a timing chart of each signal in FIG. 9 when signal N2 is at L level.

Signal M1 is L level, signal N is H level, signal N.

When the 1 signal S goes to H level when S is at L level, 7 rip 70 Tub 52.
54 is set.

When the flip-flops 52 and 54 are set, this 7
Lip 70 tubes 52 and 54 set their output to H level without synchronizing with the input clock signal, and when the signal S falls and becomes L level, the output goes to L level in synchronization with the fall of the input clock signal. Make it.

Due to the operation of these flip-flops 52 and 54, the frequency division ratio is changed, and the output signal Q of the flip-flop 55 is changed.

The period of is modulated.

This signal 4. According to the adjustment of the period, the period of the signal S and further the period of the signal R are changed.

The frequency of signal R at this time is set to 712 Hz. In this way, the programmable frequency divider circuit 9
By inputting the frequency indication signals R, , L from M6, it outputs a signal R having four different frequencies.

Figure 15 shows the volume variable circuit 10 and sound generator 1 shown in Figure 1.
1 is a diagram showing a detailed circuit configuration of No. 1. FIG.

The volume variable circuit 10 inputs the frequency signal R from the programmable frequency dividing circuit 9 to the - input terminal, and inputs the ROM from the programmable frequency dividing circuit 9 to the other input terminal.
The output signals U6-U of the Nantes gates 62-67 determine whether or not current should flow through the resistors 74-79. P-channel transistors 68 to 76.

Assuming that the total current is 1, the resistance values of the resistors 74 to 79 are equal to the signal as shown in FIG. , L7 and the frequency signal R are combined, and the signal U, ~U, is sent to the transistor 68.
When applied appropriately to the gates of ~73, the low signals U0~U,
is a signal having the same frequency as the frequency signal R, and therefore the signal V becomes a frequency signal having a current value of the above-mentioned ratio.

The generator 11 to which this signal V is applied determines the sound volume based on the current value of the signal (2), and determines the frequency of the sound to be generated based on the frequency of the one-stroke signal V.

FIG. 17 is a diagram showing another embodiment of the present invention. Incidentally, the same parts as in the above-mentioned embodiment are given the same reference numerals.

The frequency/volume instruction signal output circuit 80 in this embodiment is comprised of a notification signal output cuff/receiver 81, a decoder 82, and K. This is because when generating a sound consisting of several frequencies and volumes, using the decoder 82 to synthesize the volume and frequency instruction signals can keep costs lower than using ROM, and the circuit can also be simplified.

The effects of the present invention are listed below.

(1) In the present invention, a small ROM-? The notification sound is synthesized by combining a decoder, a programmable frequency divider, and a variable volume circuit.
It is possible to generate a pseudo circuit such as the following with a simpler circuit than the conventional one.

(2) Since a repetition counter is added to the circuit according to the present invention, the same notification sound can be repeatedly generated many times.

(3) In the present invention, there are no mechanical components, and integration is easy, and miniaturization and cost reduction are possible.

(4) The chip area can be made smaller than that of the conventional circuit system (one that uses a waveform ROM).

(5) In the present invention, the sounds of black crickets (birds) and crickets (insects) can be generated in addition to parentheses by only slightly changing the storage contents of the ROM and the configuration of the decoder. It can improve your sexuality. As described above, the present invention provides a more simplified notification sound generation circuit that generates a simulated sound such as a bird's voice using nine circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of notification sound data, FIG. 3 is a diagram showing a detailed circuit configuration of the start signal generating circuit means shown in FIG. 1, and FIG. 4 is a timing chart of each signal in FIG. 3, FIG. 5 is a diagram showing a detailed circuit configuration of the address counter shown in FIG. 1, FIG. 6 is a timing chart of each signal in FIG. 5, and FIG. is a diagram showing the details of the input/output of the ROM shown in FIG. 1, FIG. 8 is a diagram showing an example of the output state of the ROM shown in FIG. Figures 10 to 14 are diagrams showing the detailed circuit configuration of the circuit, Figures 10 to 14 are timing charts for each signal in Figure 9, and Figure 15 is a detailed diagram of the volume variable circuit and sound generator shown in Figure 1. FIG. 16 is a diagram showing the circuit configuration and a timing chart of each signal in FIG. 15. FIG. 17 is a block diagram showing another embodiment of the present invention. 1...Reference signal generation circuit, 2...Dividing circuit, 6...
・Clock drive circuit, 4.80... Frequency/volume instruction signal output circuit, 5... Address counter, 6... ROM
, 7... Start signal generation circuit, 8... Repeat kakunta, 8'... Alarm circuit, 9... Programmable frequency divider, 10... Volume variable circuit, 11... Sound generation 81... Notification signal output counter, 82... Decoder. Indication Patent No. 1857-63103 No. 2 in the case of the Director of the Japan Patent Office, Blind Kazuo Wakasugi Title of the invention Hour hand notification sound generation circuit 5 Person making the amendment Related to the case Patent applicant Address 2-27 Taito, Taito-ku, Tokyo Number 7 Name: Rhythm Watch Industry Co., Ltd. Address: 407, Niney Tamura Trio Building, 6-21-1 Honkomagome, Bunkyo-ku, Tokyo Name: Patent Attorney (6565) Ko Kawai Department:
& Column for detailed explanation of the invention in the specification to be amended & Contents of the amendment (1) In the 20th line of page 5 of the specification, the phrase “count again” was replaced with “count again” 1#rfi piece (2) ``Timing chart'' on page 9 of the specification @ line 3 K is corrected to ``timing chart.''that's all

Claims (1)

[Scope of Claims] (1) A reference signal generation circuit; a frequency division circuit that divides the signal from the reference signal generation circuit; a start signal generation circuit means for starting a notification operation; and a wrinkle start signal generation circuit means and a frequency/volume instruction signal output circuit that outputs a frequency instruction signal and a volume instruction signal in response to a signal from the frequency divider circuit and a signal from the frequency divider circuit in response to the frequency instruction signal; a programmed 2-map frequency divider that divides the frequency of the frequency signal and outputs a frequency signal; a volume variable circuit that varies the current value of the frequency signal in response to the volume instruction signal; and a volume variable circuit that responds to the signal from the volume variable circuit. 1. An alarm sound generation circuit for a watch, comprising: a sound generation circuit that generates a sound. (2) The frequency/volume instruction signal generation circuit line, a ROM that stores continuously changing frequency data, volume data, and pause data, a signal from the start signal generation circuit means, and a signal from the frequency dividing circuit. 2. The alarm sound generation circuit for a watch according to claim 1, wherein the circuit is similar to an address counter that outputs a frequency instruction signal and a volume instruction signal from the ROM in response to the ROM. (s) the frequency/volume instruction signal generation circuit includes a notification signal output counter that counts in response to the signal from the start signal generation circuit means and the signal from the frequency dividing circuit;
2. The timepiece notification generation circuit according to claim 1, further comprising a decoder that converts the signal from the wrinkle notification signal output counter into a frequency instruction signal and a volume instruction signal. (4) The start signal generation circuit means includes an alarm circuit, and a circuit for generating an alarm sound for the hour hand to generate a start signal and a repetition signal in response to a signal from the alarm circuit and a signal from the frequency dividing circuit.