JPS61240669A - 半導体集積回路 - Google Patents

半導体集積回路

Info

Publication number
JPS61240669A
JPS61240669A JP60081831A JP8183185A JPS61240669A JP S61240669 A JPS61240669 A JP S61240669A JP 60081831 A JP60081831 A JP 60081831A JP 8183185 A JP8183185 A JP 8183185A JP S61240669 A JPS61240669 A JP S61240669A
Authority
JP
Japan
Prior art keywords
channel
electrode
semiconductor integrated
ground electrode
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60081831A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0523067B2 (enrdf_load_stackoverflow
Inventor
Tetsuo Asano
哲郎 浅野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP60081831A priority Critical patent/JPS61240669A/ja
Publication of JPS61240669A publication Critical patent/JPS61240669A/ja
Publication of JPH0523067B2 publication Critical patent/JPH0523067B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/63—Combinations of vertical and lateral BJTs

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP60081831A 1985-04-17 1985-04-17 半導体集積回路 Granted JPS61240669A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60081831A JPS61240669A (ja) 1985-04-17 1985-04-17 半導体集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60081831A JPS61240669A (ja) 1985-04-17 1985-04-17 半導体集積回路

Publications (2)

Publication Number Publication Date
JPS61240669A true JPS61240669A (ja) 1986-10-25
JPH0523067B2 JPH0523067B2 (enrdf_load_stackoverflow) 1993-03-31

Family

ID=13757418

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60081831A Granted JPS61240669A (ja) 1985-04-17 1985-04-17 半導体集積回路

Country Status (1)

Country Link
JP (1) JPS61240669A (enrdf_load_stackoverflow)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5984542A (ja) * 1982-11-08 1984-05-16 Nec Corp 高周波半導体集積回路

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5984542A (ja) * 1982-11-08 1984-05-16 Nec Corp 高周波半導体集積回路

Also Published As

Publication number Publication date
JPH0523067B2 (enrdf_load_stackoverflow) 1993-03-31

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