JPS61240669A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To absorb a leakage current from an output transistor into a ground electrode irrespective of other wiring, by dividing the power source electrode and by surrounding the output transistor by the ground electrode to which the source electrode is connected through cross wiring. CONSTITUTION:Output transistors of a first channel of the semiconductor integrated circuit consist of two NPN transistors 1, 2 arrayed side by side, constituting SEPP (single end push-pull). The output transistors are surrounded by respective separating regions to be separated. The ground electrode 14 which surrounds three sides of the output transistors of each channel is made ohmic contact to the separating regions, and the power source electrode is divided and extended. Wiring to small-signal circuits of each channel from the power source electrodes 7, 15 adopts cross wiring structure. The ground electrode 14 is connected through the cross wiring which utilizes the separating regions under the power source electrodes 7, 15. Leakage current from the respective NPN transistors 1, 2 is directly absorbed into the ground electrode 14 through the separating regions.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor integrated circuit, and more particularly to an improvement in a semiconductor integrated circuit incorporating a two-channel amplifier circuit.

(b) Conventional technology It is difficult to form high-voltage transistors in semiconductor integrated circuits due to their structure, and B
It is often used to create an output amplifier using a TL connection. Such known documents and [2] "Stereo Reproducing Device", written by Ken Suzuki, published by Nikkan Kogyo Shimbun (November 1970), Volume 1
BTL connections are described on page 89.

In general, BTL connections are of the output split type (third
There are two types: the NF floating type (Fig. 4) and the NF floating type (Fig. 4). The output split type BTL connection is the input terminal I of the non-inverting amplifier 61).
An input signal is applied to N, the feedback terminal NF is grounded via a capacitor, and an output signal is obtained from the output terminal OUT. On the other hand, the input terminal IN of the inverting amplifier (01) is grounded, and the output signal of the non-inverting amplifier (01) is fed back to the feedback terminal NF via a dividing resistor and a capacitor. The load RL is connected between the output terminals of both amplifiers G9 (c) to obtain twice the output signal.

The NF floating type BTL connection is applied to the input terminal IN of the non-inverting amplifier 6D.
Ground the input terminal IN of A), connect the feedback terminal NF of A) to both amplifiers 09 with a capacitor and resistor, and connect both amplifiers 0 to (
A load R, , is connected between the output terminal OUT of (b).

In a semiconductor integrated circuit incorporating a two-channel amplifier circuit with BTL connection as described above, the output transistor of each channel amplifier circuit is formed as shown in FIG. The output transistor of the first channel amplifier circuit is formed in the upper half of the chip, and the output transistor of the second channel amplifier circuit is formed in the lower half of the chip.

The output transistor of the first channel is formed by two NPN transistors arranged on the left and right, which are connected to the transistor 01) to form a 5EPP (single-ended push-pull). The collector electrode of the left NPN transistor 01) is the Vcc power supply electrode (
b) is connected to the base electrode, the emitter electrode) is connected to the output terminal (4η) of the first channel, and the collector electrode of the NPN transistors θ on the right ( The electrode 0' is connected to the output terminal 0'i) of the first channel, the base electrode 00 is connected to the amplifying circuit at the previous stage, and the emitter electrode 2 is connected to the ground electrode 51). Note that the output transistor of the second channel is also formed line-symmetrically with the first channel. The equivalent circuit is shown in FIG.

In such a semiconductor integrated circuit, the output transistors of each channel are surrounded and separated by isolation regions, and a ground electrode 51) in ohmic contact with the isolation region is provided on the isolation region at the right end of the chip. It was formed in common for all channels.

(c) Problems to be solved by the invention However, in such a semiconductor integrated circuit, the ground electrode 15
1) is contacted only in the isolation region at the right end of the chip, so the parasitic current of the output transistor that handles large currents cannot be sufficiently sucked out from the ground electrode 61), which has the disadvantage that parasitic effects are likely to occur. .

B) Means for Solving the Problems The present invention has been made in view of such drawbacks, and the ground electrode t51
) by surrounding the output transistor of each channel, the aim is to realize a semiconductor integrated circuit that greatly improves the conventional drawbacks.

(E) Effect According to the present invention, by surrounding the output transistor of each channel with the ground electrode Gυ, the leakage current from the output transistor can be immediately sucked out by the ground electrode 61) which is electrically connected to the substrate, and parasitic effects can be prevented. It is.

(F) Embodiment An embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

A semiconductor integrated circuit according to the present invention is formed by incorporating a two-channel amplifier circuit, and the output transistor of the amplifier circuit of each channel is formed as shown in FIG.

That is, the first channel amplifier circuit is formed in the upper half of the step, and consists of the first channel small signal circuit located on the left side and the output transistor located on the right side, and the second channel amplifier circuit has a similar arrangement. is formed in the lower half of the chip. The output transistor of the first channel consists of two NPN ) transistors (1) (
2), and these transistors (1) and (2) are 5E
They are connected to form a PP (single-ended pushpull). Each transistor has a plurality of base regions (4) and emitter regions (5) formed in a collector region (3) indicated by a solid line.1. , the desired connections are made with the electrodes indicated by dotted lines. The collector electrode (6) of the left NPN ) transistor (1) is connected to the first Vcc power supply electrode (7), the base electrode (8) is connected to the previous stage small signal amplifier circuit, and the emitter electrode ( 9) is connected to the output terminal α1 of the first channel. The NPN transistor on the right (
The collector electrode (b) of 2) is connected to the output terminal (g) of the first channel, the base electrode @ is connected to the small signal amplifier circuit in the previous stage, and the emitter electrode (g) is connected to the common ground for both channels. Connected to electrode α→. Note that the output transistor of the second channel is also formed line-symmetrically with the first channel.

A feature of the present invention lies in the arrangement of the ground electrodes.

The output transistors of each channel are surrounded and separated by isolation regions, and the ground electrode α surrounds three sides of the output transistor of each channel. These three sides are the three sides excluding the upper side of the first channel output transistor and the lower side of the second channel output transistor. The six ground electrodes are in ohmic contact with the isolation region below, and the Vcc power supply electrode, which has been common in the past, is divided and extended between them. Note that the wiring from the first and second Vcc power supply electrodes (to) Qe to the small signal circuits for each channel employs a cross wiring structure as shown in FIG. In Figure 2, the wire is a P-type semiconductor substrate, and 01) is an N-type semiconductor substrate.
P+ type isolation region diffused in W epitaxial layer, (a) is oxide film, 0-1 ground electrode, (7) (to) is first
and a second Vcc power supply electrode. With the above structure, the ground electrode Q41 is connected to all three sides via cross wiring, and is connected to an external pin via a bonding wire from the ground electrode (l→) provided at the right end of the chip. Since a large-area isolation region Q1) under the second Vcc power supply electrode (7) is used, a conductive bus with considerably low resistance can be formed, and the six separated ground electrodes can be connected with low resistance. There is. The first and second Vcc power supply electrodes (7
) A wiring line is formed from Qe to the small signal circuit of each channel.

According to the structure of the present invention described above, the output transistors of each channel, that is, two NPN) transistors (1) (2)
) is surrounded by six ground electrodes on three sides except the top or bottom, and the leakage current from each NPN transistor (1) and (2) immediately flows through the separation area to the ground electrode α →
is sucked out.

Note that the side on which the ground electrode is not provided is adjacent to the top or bottom side of the chip, so there is little risk of leakage current flowing to the small signal circuit, and the wiring to the previous small signal circuit is derived from this side. There is.

(g) Effects of the Invention According to the present invention, since the power supply electrode is divided and three sides of the output transistor of each channel are surrounded by the ground electrode 04, the leakage current of the output transistor can be immediately absorbed by the ground electrode 0. , which has the advantage of preventing parasitic effects.

Also, since the wiring layer (to) from the power supply electrode (7) (to) and the ground electrode α have a cross wiring structure, the output transistor of each channel is surrounded by the ground electrode a → regardless of other wiring. It has the advantage of having fewer design restrictions.

Furthermore, in the present invention, the cross wiring is connected to the first and second power supply electrodes.
(7) Since it is formed in the lower isolation region, it does not require extra space and has the advantage of preventing an increase in pattern area.

Furthermore, the present invention has the advantage that a BTL-connected two-channel amplifier circuit can be stably obtained, and the range of application of semiconductor integrated circuits can be greatly expanded.

[Brief explanation of the drawing]

Fig. 1 is a top view illustrating a semiconductor integrated circuit according to the present invention, Fig. 2 is a sectional view illustrating a cross wiring structure used in the present invention, and Figs. 3 and 4 are illustrating general TL connections. FIG. 5 is a top view illustrating a conventional semiconductor integrated circuit, and FIG. 6 is an equivalent circuit diagram of FIG. Explanation of main drawing numbers (1) (2) are NPN) transistors, (7) is 1st
00 is the output terminal of the first channel, (14) & is the ground electrode, and Qe is the second Vcc power electrode.

Claims (1)

[Claims] (1) In a semiconductor integrated circuit incorporating a two-channel amplifier circuit including an output transistor forming a SEPP (single-ended push-pull) circuit, ohmic contact is made with the isolation region surrounding the output transistor of each amplifier circuit. A ground electrode is provided, a power supply electrode common to the output transistors of each amplifier circuit is divided by the ground electrode, and the ground electrode divided by the wiring line from the power supply electrode is crossed over using a separation area provided under the power supply electrode. 1. A semiconductor integrated circuit characterized by being connected in a straight line.