JPS61214444A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS61214444A
JPS61214444A JP60055264A JP5526485A JPS61214444A JP S61214444 A JPS61214444 A JP S61214444A JP 60055264 A JP60055264 A JP 60055264A JP 5526485 A JP5526485 A JP 5526485A JP S61214444 A JPS61214444 A JP S61214444A
Authority
JP
Japan
Prior art keywords
chip
substrate
semiconductor
package
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60055264A
Other languages
English (en)
Inventor
Masahiro Sugimoto
杉本　正浩
Teruyuki Nabeta
鍋田　照行
Shigeki Harada
茂樹 原田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60055264A priority Critical patent/JPS61214444A/ja
Publication of JPS61214444A publication Critical patent/JPS61214444A/ja
Pending legal-status Critical Current

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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は半導体装置に係り、そのうち、特に半導体組立
構造に関する。
ＩＣなどの半導体装置は、ウェハープロセスを経て半導
体チップが形成され、その半導体チップが半導体容器（
パッケージ）に収容され、それぞれの端子間を配線（ワ
イヤーボンディング）して、半導体装置に完成される。
しかし、ワイヤーボンディングは、多数の端子間を１本
づつボンディングする方式であるから、工数が多くかか
る欠点があり、また、そのために自動ボンディング機を
使用すると、その設備投資が増加する問題がある。
従って、従前より、この配線方法について種々検討され
てきたが、現在、最善の方法として自動ワイヤーボンデ
ィング法が汎用されている。また、一部には、テープキ
ャリア方式のような銅パターンを張り付ける方法も用い
られている。しかし、出来得るならば、一層簡易な配線
方法が望ましいことは云うまでもない。
［従来の技術］ 第３図は従来の半導体装置の断面構造を示しており、本
例は一般的なボンディングワイヤ°−による接続構造で
ある。１はアルミナ製のセラミックパッケージ、２は半
導体チップ（以下、チップと呼ぶ）、３はボンディング
ワイヤー、４はキャップである。チップとパッケージと
は半田、樹脂またはガラスで接着されており、ボンディ
ングワイヤー３は２０〜３０μｍの金線またはアルミニ
ウム線が用いられて、チップ上のバンド（端子）５とパ
ッケージ上のパターン（端子）６とを熱圧着や超音波圧
着で接続している。かようなワイヤーボンディング方式
が、現在、自動化され、汎用されている方式である。
次に、第４図は他の接続構造の半導体装置の部分断面で
、銅膜パターン７を半田付けして、チップ上のパッド（
端子）５とパッケージ上のパターン（端子）６とを接続
している。それには、銅膜を予めエツチングしてパター
ンを作成し、その銅膜パターン７をチップ２のパッド５
に半田付けした後、パッケージｌのパターン６に半田付
けする順序で接続される。
前者のワイヤーボンディングは１本づつワイヤーが接続
されるが、この銅膜パターン方式は全パターンを同時に
半田付けする方法を採ることができ、処理工数は銅膜パ
ターン方式の方がはるかに少なくなる。
［発明が解決しようとする問題点コ ところで、上記したように、ワイヤーボンディング法は
手作業によると工数が増大し、自動化すると設備投資が
増加する問題がある。
また、銅膜パターンの半田付は法は処理工数が低減され
るが、微細な配線が困難な欠点がある。
本発明は、このような問題点を除去した半導体装置の構
造を提案するものである。
［問題点を解決するための手段］ その問題は、半導体パッケージと半導体チップとの間隙
が有機絶縁樹脂で埋められ、該有機絶縁樹脂面を含む面
上を横切って、前記半導体パッケージの端子と半導体チ
ップの端子とが薄膜パターンで接続されている半導体装
置によって解決される。
同様に、半導体パッケージ面が有機絶縁樹脂で被覆され
、且つ、該半導体パッケージと半導体チップとの間隙、
が有機絶縁樹脂で埋められ、該有機絶縁樹脂面を含む面
上を横切って、前記半導体パッケージの端子と半導体チ
ップの端子とが薄膜パターンで接続されている半導体装
置によっても解決される。
［作用］ 即ち、本発明は半導体チップと半導体パッケージとの間
隙を有機絶縁―脂で埋めて平坦化した後、ウェハープロ
セスと同様に、蒸着またはスパッタによって銅薄膜を被
着させ、これをパターンニングして配線を形成するもの
である。
そうすると、総ての配線を一度にパターンニングできて
工数が低減され、且つ、微細な配線が可能になる。また
、設備投入も不要になる。
［実施例］ 以下、図面を参照して実施例によって詳細に説明する。
第１図は本発明にかかる半導体装置の部分断面図を示し
ており、１１はパッケージ基板、１２はポリイミド、１
３は薄膜パターン、その他の記号は第３図、第４図と同
様である。ポリイミド１２はチップ２とパッケージ基板
１１の間を埋めて、表面を両者と同様の高さにして平坦
化しである。従って、その上に銅の薄膜を蒸着しても、
段差による断線の心配がなく、１〜数μｍの銅膜を被着
して、フォトプロセスによってパターンニングすること
ができる。銅膜のエツチングには塩化第２鉄溶液が用い
られる。
但し、パッケージ基板はチップと熱膨張率が近似してい
ることが望ましい。それには、シリコンカーバイド（Ｓ
ｉＣ）基板が良く、且つ、ＳｉＣ基板は熱伝導性も良い
ので最適材料である。そうすれば、チップとポリイミド
の熱膨張率は近似しており、又、パッケージ基板とも近
似しているから、動作中に高温度に昇温しても薄膜パタ
ーン１３の断線の心配がなく、配線の信頼性は高められ
る。
次に、第２図は本発明にかかる他の半導体装置の部分断
面図を示しており、１２°はポリイミド。
１３°は薄膜パターン、その他の記号は第１図と同様で
ある。本例はチップ２とＳｉＣ基板１１の間をボリイミ
ド１２゛で埋めるだけでなく、ＳｉＣ基板の表面にもポ
リイミド１２“を塗布しており、その理由はＳｉＣ基板
が絶縁性が十分でないからである。
それには、チ・７プ２をＳｉＣ基板１１に接着した後、
ポリイミド１２′を塗布してプレベークし、端子（パ・
２ド１パターンなど）を露出するためのパターンニング
を行なう。次いで、熱処理してポリイミドを硬化させた
後、次に、ｗ４薄膜を被着してパターンニングする。こ
の時、チップ上にポリイミドが被着しても問題はなく、
むしろα線対策でチップ面に塗布する場合も多い。
このようにすれば、銅薄膜パターンからなる配線を形成
することができて、同時に多数の微細配線パターンが作
成できる。従って、処理工数が軽減され、製造設備も安
価になる。
〔発明の効果］ 以上の説明から明らかなように、本発明によれば一括し
て微細配線を作成することができて、スループットの向
上に役立つ。且つ、製造設備に大きな投資をする必要も
なく、また、配線に必要な信頼も得られる。
【図面の簡単な説明】
第１図および第２図は本発明にかかる半導体装置の部分
断面図、 第３図は従来の半導体装置の断面図、 第４図は従来の他の半導体装置の部分断面図である。 図において、 １はアルミナパッケージ、 ２は半導体チップ、 ３はボンディングワイヤー、 ５はチップ上のパッド（端子）、 ６はパッケージ上のパターン（端子）、７は銅膜パタ、
−ン、 １１はＳｉＣ基板（パッケージ）、 １２．１２’はポリイミド、 １３．１３’は薄膜パターン を示している。 ／Ｖ−発明峠犀傅装置め昂扮酢面図 Ｉｌｌ　　図 ／Ｉ１１項ぢ咽めイむ半ｊ１夕奈袈１の射昂１１ｆｆｉ
！＄　２　図 従Ｊ４半導体装蓄山鉾面区 第３図 りｔ来ｎ矛と／）〒１１ルトｉｔの多矛４１防１行図第
４図

Claims (2)

    【特許請求の範囲】
  1. （１）、半導体パッケージと半導体チップとの間隙が有
    機絶縁樹脂で埋められ、該有機絶縁樹脂面を含む面上を
    横切つて、前記半導体パッケージの端子と半導体チップ
    の端子とが薄膜パターンで接続されていることを特徴と
    する半導体装置。
  2. （２）、半導体パッケージ面が有機絶縁樹脂で被覆され
    、且つ、該半導体パッケージと半導体チップとの間隙が
    有機絶縁樹脂で埋められ、該有機絶縁樹脂面を含む面上
    を横切つて、前記半導体パッケージの端子と半導体チッ
    プの端子とが薄膜パターンで接続されていることを特徴
    とする半導体装置。
JP60055264A 1985-03-18 1985-03-18 半導体装置 Pending JPS61214444A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60055264A JPS61214444A (ja) 1985-03-18 1985-03-18 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60055264A JPS61214444A (ja) 1985-03-18 1985-03-18 半導体装置

Publications (1)

Publication Number Publication Date
JPS61214444A true JPS61214444A (ja) 1986-09-24

Family

ID=12993738

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60055264A Pending JPS61214444A (ja) 1985-03-18 1985-03-18 半導体装置

Country Status (1)

Country Link
JP (1) JPS61214444A (ja)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5605863A (en) * 1990-08-31 1997-02-25 Texas Instruments Incorporated Device packaging using heat spreaders and assisted deposition of wire bonds
JP2001313467A (ja) * 2000-02-21 2001-11-09 Ngk Spark Plug Co Ltd 配線基板
EP1243025A2 (en) * 1999-09-30 2002-09-25 Alpha Industries, Inc. Semiconductor packaging
JP2007510301A (ja) * 2003-10-29 2007-04-19 コンダクティブ・インクジェット・テクノロジー・リミテッド 部品の電気的接続
JP2007324429A (ja) * 2006-06-02 2007-12-13 Murata Mfg Co Ltd モジュール部品及びその製造方法
JP2013115070A (ja) * 2011-11-25 2013-06-10 Fuji Mach Mfg Co Ltd 半導体パッケージ及びその製造方法
WO2013168223A1 (ja) * 2012-05-08 2013-11-14 富士機械製造株式会社 半導体パッケージ及びその製造方法
JP2014003177A (ja) * 2012-06-19 2014-01-09 Fuji Mach Mfg Co Ltd 半導体パッケージ及びその製造方法
JP2014003176A (ja) * 2012-06-19 2014-01-09 Fuji Mach Mfg Co Ltd 半導体パッケージ及びその製造方法

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5605863A (en) * 1990-08-31 1997-02-25 Texas Instruments Incorporated Device packaging using heat spreaders and assisted deposition of wire bonds
EP1243025A2 (en) * 1999-09-30 2002-09-25 Alpha Industries, Inc. Semiconductor packaging
JP2001313467A (ja) * 2000-02-21 2001-11-09 Ngk Spark Plug Co Ltd 配線基板
JP4685979B2 (ja) * 2000-02-21 2011-05-18 日本特殊陶業株式会社 配線基板
JP2007510301A (ja) * 2003-10-29 2007-04-19 コンダクティブ・インクジェット・テクノロジー・リミテッド 部品の電気的接続
JP2007324429A (ja) * 2006-06-02 2007-12-13 Murata Mfg Co Ltd モジュール部品及びその製造方法
JP2013115070A (ja) * 2011-11-25 2013-06-10 Fuji Mach Mfg Co Ltd 半導体パッケージ及びその製造方法
WO2013168223A1 (ja) * 2012-05-08 2013-11-14 富士機械製造株式会社 半導体パッケージ及びその製造方法
JPWO2013168223A1 (ja) * 2012-05-08 2015-12-24 富士機械製造株式会社 半導体パッケージ及びその製造方法
JP2014003177A (ja) * 2012-06-19 2014-01-09 Fuji Mach Mfg Co Ltd 半導体パッケージ及びその製造方法
JP2014003176A (ja) * 2012-06-19 2014-01-09 Fuji Mach Mfg Co Ltd 半導体パッケージ及びその製造方法

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