JPS61214435A - Formation of pattern for wet etching - Google Patents

Formation of pattern for wet etching

Info

Publication number
JPS61214435A
JPS61214435A JP5502085A JP5502085A JPS61214435A JP S61214435 A JPS61214435 A JP S61214435A JP 5502085 A JP5502085 A JP 5502085A JP 5502085 A JP5502085 A JP 5502085A JP S61214435 A JPS61214435 A JP S61214435A
Authority
JP
Japan
Prior art keywords
resist
pattern
oxide film
negative resist
positive resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5502085A
Other languages
Japanese (ja)
Inventor
Yuji Ashikaga
足利　祐司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP5502085A priority Critical patent/JPS61214435A/en
Publication of JPS61214435A publication Critical patent/JPS61214435A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching

Abstract

PURPOSE:To improve the tightness of contact at wet etching of a negative resist and to improve the resolution of patterning of a silicon substrate by patterning the negative resist by using the positive resist as a mask when patterning the silicon substrate. CONSTITUTION:An oxide film 2 is formed on a silicon substrate 1 and this film 2 is coated with a negative resist 3 and a positive resist 4. The mask on which a circuit pattern is formed is irradiated with the light to pattern the positive resist 4. The negative resist 3 is patterned by O2 plasma by using the positive resist 4 as a mask thereby forming a pattern (b). The part of oxide film 2 where a film of the negative resist 3 was removed is subjected to wet etching to expose a pattern (c). The negative resist 3 and the positive resist 4 are removed from the oxide film 2 to form the silicon substrate 1 having the pattern (c).

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は、ウェットエツチングにより回路基板にパター
ンを形成するパターン形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a pattern forming method for forming a pattern on a circuit board by wet etching.

（従来の技術） 従来のこの種のパターン形成は、次のような方法で行な
われている。シリコン基板上に５ｉｄｅの酸化膜を熱酸
化などにより形成した後、その酸化膜上にポジ型レジス
トまたはゴム系のネガ型レジストを形成する。このよう
にして形成した基板のパターンニングは、前記ポジ型レ
ジストまたは前記ネガ型レジストをパターンニングし、
次いで前記酸化膜をウェットエツチングする。これによ
り、前記シリコン基板上には回路パターンが形成される
ことになる。(Prior Art) Conventionally, this type of pattern formation is performed by the following method. After forming a 5-ide oxide film on a silicon substrate by thermal oxidation or the like, a positive resist or a rubber-based negative resist is formed on the oxide film. Patterning of the substrate formed in this way involves patterning the positive resist or the negative resist,
Next, the oxide film is wet etched. As a result, a circuit pattern is formed on the silicon substrate.

しかしながら、前記ポジ型レジストは高解像度のパター
ンニングが可能であるが、ウェットエツチングを行う際
の前記酸化膜との密着性が悪い。However, although the positive resist allows for high-resolution patterning, it has poor adhesion to the oxide film during wet etching.

また、前記ゴム系ネガ型レジストは、ウェットエツチン
グを行う際の前記密着性が良いが、シリコン基板のパタ
ーンニングを行う際の解像度が低い。Further, the rubber-based negative resist has good adhesion when performing wet etching, but has low resolution when patterning a silicon substrate.

（発明が解決しようとする問題点） 本発明は、このような事情に鑑みてなされたものであっ
て、ネガ型レジストのウェットエツチング時の密着性を
向上させ、シリコン基板のパターンニングの解像度を上
げることができるウェットエツチングのためのパターン
形成方法を提供することを目的とする。(Problems to be Solved by the Invention) The present invention has been made in view of the above circumstances, and aims to improve the adhesion of a negative resist during wet etching and improve the resolution of patterning on a silicon substrate. It is an object of the present invention to provide a pattern forming method for wet etching that can be improved.

（問題点を解決するための手段） 本発明は、このような目的を達成するために、シリコン
基板上に酸化膜を形成し、前記酸化膜上にネガ型レジス
トを塗−布し、さらに前記ネガ型レジスト上にポジ型レ
ジストを塗布してなる基板をパターンニングする際、前
記ポジ型レジストをパターンニングし、前記ポジ型レジ
ストをマスクとして前記ネガ型レジストをパターンニン
グし、次いで前記酸化膜をエツチングし、その後前記ポ
ジ型レジストと前記ネガ型レジストとを前記酸化膜から
剥離するようにしている。(Means for Solving the Problems) In order to achieve the above object, the present invention forms an oxide film on a silicon substrate, coats a negative resist on the oxide film, and further applies the When patterning a substrate formed by coating a positive resist on a negative resist, the positive resist is patterned, the negative resist is patterned using the positive resist as a mask, and then the oxide film is patterned. After etching, the positive resist and the negative resist are peeled off from the oxide film.

（実施例） 以下、本発明を図面に示す実施例に基づいて詳細に説明
する。第１図ないし第６図は、本発明の詳細な説明する
ための簡略化した基板の構造断面図である。(Example) Hereinafter, the present invention will be described in detail based on an example shown in the drawings. 1 to 6 are simplified structural cross-sectional views of a substrate for explaining the present invention in detail.

シリコン基板ｌ上には熱酸化により５ｉＯａなどの酸化
膜２を形成し、その酸化膜２上に感光性のあるエステル
系、例えばゴム系のネガ型レジスト３を塗布し、そのネ
ガ型レジスト３を乾燥させることにより第１図に示す構
造の基板を形成する。An oxide film 2 of 5iOa or the like is formed on the silicon substrate l by thermal oxidation, and a photosensitive ester-based, for example, rubber-based negative resist 3 is applied onto the oxide film 2. By drying, a substrate having the structure shown in FIG. 1 is formed.

さらに第２図に示すように、そのネガ型レジスト３上に
ポジ型レジスト４を塗布する。次に、予め定めた回路パ
ターンが形成されたマスク（図示仕ず）を前記ポジ型レ
ジスト４上に位置させる。そのマスクに光を照射して、
前記ポジ型レジスト４のパターンニングを行う。これに
より前記マスクの透過部分に対応する第３図に示すパタ
ーンａを形成するためにポジ型レジスト４の現像を行う
。Furthermore, as shown in FIG. 2, a positive resist 4 is applied onto the negative resist 3. Next, a mask (not shown) on which a predetermined circuit pattern is formed is placed on the positive resist 4. Irradiate the mask with light,
The positive resist 4 is patterned. Thereby, the positive resist 4 is developed to form a pattern a shown in FIG. 3 corresponding to the transparent portion of the mask.

即ち前記マスクの黒色部分は光を透過せず、その他の部
分は光を透過させ、ポジ型レジスト４を感光させる。し
たがってポジ型レジスト４が感光された部分が現像によ
り除去されることになる。That is, the black portion of the mask does not transmit light, and the other portions transmit light, thereby exposing the positive resist 4 to light. Therefore, the exposed portion of the positive resist 4 is removed by development.

次に、前記ポジ型レジスト４をマスクとして、ネガ型レ
ジスト３を０．プラズマによりパターンニングし第４図
に示すようにパターンｂを形成する。次に、前記ネガ型
レジスト３の膜が無くなった酸化膜２の部分をウェット
エツチングし、第５図に示すようにシリコン基板ｌの表
面、即ちパターンＣを露出させる。次に、ネガ型レジス
ト３およびポジ型レジスト４を酸化膜２から剥離し、こ
れにより第６図に示すようなパターンＣを宵するシリコ
ン基板ｌを形成する。Next, using the positive resist 4 as a mask, apply a negative resist 3 of 0.000. Patterning is performed using plasma to form pattern b as shown in FIG. Next, the portion of the oxide film 2 where the film of the negative resist 3 is removed is wet-etched to expose the surface of the silicon substrate 1, that is, the pattern C, as shown in FIG. Next, the negative resist 3 and the positive resist 4 are peeled off from the oxide film 2, thereby forming a silicon substrate 1 having a pattern C as shown in FIG.

（発明の効果） 以上のように本発明によれば、シリコン基板上に酸化膜
を形成し、前記酸化膜上にネガ型レジストを塗布し、さ
らに前記ネガ型レジスト上にポジ型レジストを塗布して
なる基板を形成し、その基板から前記シリコン基板をパ
ターンニングする際、前記ポジ型レジストをマスクとし
て前記ネガ型レジストをパターンニングするようにした
ので、前記ネガ型レジストのウェットエツチング時の密
着性が向上し、前記シリコン基板のパターンニングの解
像度が上がる等の効果が発揮される。(Effects of the Invention) As described above, according to the present invention, an oxide film is formed on a silicon substrate, a negative resist is applied on the oxide film, and a positive resist is further applied on the negative resist. When patterning the silicon substrate from the substrate, the negative resist is patterned using the positive resist as a mask, so that the adhesion of the negative resist during wet etching is improved. Effects such as improved resolution of patterning of the silicon substrate are exhibited.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ないし第６図は、本発明の詳細な説明するための
簡略化した構造断面図である。 １・・・シリコン基板、２・・・酸化膜、３・・・ネガ
型レジスト、４・・・ポジ型レジスト。1 to 6 are simplified structural cross-sectional views for explaining the present invention in detail. 1... Silicon substrate, 2... Oxide film, 3... Negative resist, 4... Positive resist.

Claims (1)

【特許請求の範囲】[Claims] （１）シリコン基板上に酸化膜を形成し、前記酸化膜上
にネガ型レジストを塗布し、さらに前記ネガ型レジスト
上に、ポジ型レジストを塗布してなる基板を、パターン
ニングする際、前記ポジ型レジストをパターンニングし
、前記ポジ型レジストをマスクとして前記ネガ型レジス
トをパターンニングし、次いで前記酸化膜をエッチング
し、その後前記ポジ型レジストと前記ネガ型レジストと
を前記酸化膜から剥離することを特徴とするウェットエ
ッチングのためのパターン形成方法。(1) When patterning a substrate in which an oxide film is formed on a silicon substrate, a negative resist is applied on the oxide film, and a positive resist is further applied on the negative resist, the Patterning a positive resist, patterning the negative resist using the positive resist as a mask, etching the oxide film, and then peeling off the positive resist and the negative resist from the oxide film. A pattern forming method for wet etching characterized by:
JP5502085A 1985-03-19 1985-03-19 Formation of pattern for wet etching Pending JPS61214435A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5502085A JPS61214435A (en) 1985-03-19 1985-03-19 Formation of pattern for wet etching

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5502085A JPS61214435A (en) 1985-03-19 1985-03-19 Formation of pattern for wet etching

Publications (1)

Publication Number Publication Date
JPS61214435A true JPS61214435A (en) 1986-09-24

Family

ID=12986981

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5502085A Pending JPS61214435A (en) 1985-03-19 1985-03-19 Formation of pattern for wet etching

Country Status (1)

Country Link
JP (1) JPS61214435A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100278627B1 (en) * 1993-10-09 2001-02-01 윤종용 Manufacturing Method of Semiconductor Device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49104572A (en) * 1973-02-07 1974-10-03
JPS5483770A (en) * 1977-12-16 1979-07-04 Nec Corp Forming method for pattern during semiconductor manufacture
JPS54146966A (en) * 1978-05-10 1979-11-16 Nec Corp Pattern forming method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49104572A (en) * 1973-02-07 1974-10-03
JPS5483770A (en) * 1977-12-16 1979-07-04 Nec Corp Forming method for pattern during semiconductor manufacture
JPS54146966A (en) * 1978-05-10 1979-11-16 Nec Corp Pattern forming method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100278627B1 (en) * 1993-10-09 2001-02-01 윤종용 Manufacturing Method of Semiconductor Device

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