JPH0520515B2 - - Google Patents
Info
- Publication number
- JPH0520515B2 JPH0520515B2 JP60221188A JP22118885A JPH0520515B2 JP H0520515 B2 JPH0520515 B2 JP H0520515B2 JP 60221188 A JP60221188 A JP 60221188A JP 22118885 A JP22118885 A JP 22118885A JP H0520515 B2 JPH0520515 B2 JP H0520515B2
- Authority
- JP
- Japan
- Prior art keywords
- resist
- substrate
- film
- dry film
- curved
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010408 film Substances 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 9
- 238000000206 photolithography Methods 0.000 claims description 8
- 238000003672 processing method Methods 0.000 claims description 8
- 239000010409 thin film Substances 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/064—Photoresists
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
- C23F1/02—Local etching
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Materials Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Electronic Switches (AREA)
- ing And Chemical Polishing (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は曲面型サーマルヘツド等の曲面を有す
る基板に対してもフオトリソエツチングが行なえ
るようにしたフオトリソエツチング加工法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a photolithography processing method that allows photolithography to be performed even on a substrate having a curved surface such as a curved thermal head.
従来のフオトエツチング加工法として、例え
ば、平面に加工された絶縁基板上に電極を形成す
るための金属膜を加工するに際しては、電極を蒸
着あるいはスパツク法によつて基板上に形成のの
ち、フオトリソエツチング技術によつてパターン
を形成する方法が採られている。この場合の加工
精度は、エツチング時のマスクと基板の平滑度を
向上させることにより上げることができる。
As a conventional photoetching method, for example, when processing a metal film for forming electrodes on a flat insulating substrate, the electrodes are formed on the substrate by vapor deposition or sputtering, and then photoetching is performed. A method of forming patterns using litho etching technology has been adopted. Processing accuracy in this case can be increased by improving the smoothness of the mask and substrate during etching.
さらに、加工精度を向上させる目的をもち、パ
ターン焼付前に感光性ドライフイルムレジストに
対して帯電防止処理がされている絶縁基板上への
パターン形成方法が、特公昭59−16433号公報に
開示されている。 Furthermore, Japanese Patent Publication No. 16433/1989 discloses a method for forming a pattern on an insulating substrate in which a photosensitive dry film resist is subjected to antistatic treatment before pattern printing, with the aim of improving processing accuracy. ing.
しかし従来のフオトエツチング加工法、および
開示されている絶縁基板上へのパターン形成方法
にあつては、第３図のように曲面を有する基板１
０に従来の加工法を適用しようとする場合、平面
のマスク１１を使用すると、基板の曲面部がマス
クより離れるため、該曲面部では精度の良いパタ
ーンを形成することができない不具合がある。
However, in the conventional photoetching method and the disclosed pattern forming method on an insulating substrate, a substrate 1 having a curved surface as shown in FIG.
When applying the conventional processing method to the substrate 0, if a flat mask 11 is used, the curved portion of the substrate is separated from the mask, so there is a problem that a highly accurate pattern cannot be formed on the curved portion.
このような不具合を解決するものとして、特公
昭59−230770号に示されるようにフレキシブルマ
スクを用いる技術が提案されている。しかし、フ
レキシブルマスクを固定することが難しく、加工
精度を高めることは容易でない。 To solve this problem, a technique using a flexible mask has been proposed as shown in Japanese Patent Publication No. 59-230770. However, it is difficult to fix the flexible mask, and it is not easy to improve processing accuracy.
本発明は上記事情に鑑みてなされたものであ
り、曲面を有する基板上への導体膜形成を精度良
く行うため、被エツチング物に貼付する前に平滑
なステージ上でドライフイルムレジストに所望の
パターンを露光させた後に、曲面を有する基板上
に所望のパターンのレジストを有するドライフイ
ルムレジストのレジスト面を貼着し、現像したレ
ジストをマスクとしてエツチングするようにした
フオトリソエツチング加工法を提供するものであ
る。
The present invention has been made in view of the above circumstances, and in order to accurately form a conductive film on a substrate having a curved surface, a desired pattern is formed on a dry film resist on a smooth stage before being attached to an object to be etched. To provide a photolithography processing method in which a resist surface of a dry film resist having a desired pattern of resist is pasted onto a curved substrate after exposure, and the developed resist is used as a mask for etching. It is.
以下、本発明によるフオトリソエツチング加工
法を図面を参照して詳細に説明する。
Hereinafter, the photolithography processing method according to the present invention will be explained in detail with reference to the drawings.
第１図ａ〜ｆは本発明のフオトリソエツチング
加工法を示す。 Figures 1a-f illustrate the photolithography process of the present invention.
まず、マスクアライナーの平滑なステージ１
に、フイルム２上にレジスト層５を形成したドラ
イフイルムレジスト１５を載せ（或いはドライフ
イルムレジスト１５を平滑な薄い支持板に貼着
し、これをステージ１に載せ）る（第１図ａ参
照）。ついで、ドライフイルムレジスト１５とホ
トマスク３をアライメントし、光源４によつて露
光し、フイルム２とホトマスク３の間のレジスト
層５を露光する（第１図ｂ参照）。 First, the smooth stage 1 of the mask aligner
A dry film resist 15 with a resist layer 5 formed thereon is placed on the film 2 (or the dry film resist 15 is adhered to a smooth thin support plate and placed on the stage 1) (see Fig. 1a). . Next, the dry film resist 15 and the photomask 3 are aligned and exposed by the light source 4 to expose the resist layer 5 between the film 2 and the photomask 3 (see FIG. 1b).
更に、ホトマスク３をドライフイルムから剥が
す（第１図ｃ参照）。このとき、前記の工程にお
いて支持板を用いた場合には、支持板も剥がす。
つぎに、基板１０に予め形成されている導体薄膜
６の表面に、ドライフイルムレジスト１５のレジ
スト５面を貼着したのち、フイルム２を剥離する
（第１図ｄ参照）。 Furthermore, the photomask 3 is peeled off from the dry film (see FIG. 1c). At this time, if a support plate was used in the above step, the support plate is also peeled off.
Next, the resist 5 of the dry film resist 15 is adhered to the surface of the conductor thin film 6 previously formed on the substrate 10, and then the film 2 is peeled off (see FIG. 1d).
この工程の後、現像し（第１図ｅ参照）、レジ
ストベークののちエツチングを行うと第１図ｆに
示すようにパターンが形成される。 After this step, development is performed (see FIG. 1e), resist baking is performed, and etching is performed to form a pattern as shown in FIG. 1f.
以上のフオトリソエツチング加工法を適用して
サーマルヘツドを作成した実施例を第２図に基づ
いて説明する。 An example in which a thermal head was created by applying the above photolithography process method will be described with reference to FIG.
まず、グレーズドセラミツク基板２０の曲面部
にTa2Ｎ抵抗体２１をスパツタし（第２図ａ参
照）、このスパツタ面に前述したドライフイルム
レジストと同様のドライフイルムレジスト２２を
レジスト層を抵抗体２１に対向させ、熱ローラに
よつて、15μm厚に圧着する（第２図ｂ参照）。つ
いで、シヤワー現象を行つた（第２図ｃ参照）の
ちベークし、CF4＋O2ガスを用いたドライエツチ
ング法によつてTa2Ｎをエツチングして抵抗体２
３を形成する（第２図ｄ及びｅ）。更に、抵抗体
２３に接続される電極２４を基板２０の両面に形
成するために、NiCr−Au導体を蒸着し、この上
に上記と同様の手法によつて得たレジスト膜を形
成し、KI＋I2＋H2Ｏのエツチング液によつてAu
をエツチングするとともに、Hcl＋H2Ｏのエツチ
ング液によりNi−Crをエツチングして導体パタ
ーンを形成する（第２図ｆ）。ついで、SiO2−
Ta2O5の保護膜２５を抵抗体２３の表面に着膜す
る（第２図ｇ）ことにより、サーマルヘツドが完
成する。 First, a Ta 2 N resistor 21 is sputtered on the curved surface of a glazed ceramic substrate 20 (see FIG. 2a), and a dry film resist 22 similar to the dry film resist described above is applied to the sputtered surface to cover the resist layer 21. 2, and press it to a thickness of 15 μm using a hot roller (see Figure 2b). Next, after performing a shower phenomenon (see Fig. 2c), it is baked, and the Ta 2 N is etched by a dry etching method using CF 4 +O 2 gas to form the resistor 2.
3 (Fig. 2 d and e). Furthermore, in order to form electrodes 24 connected to the resistor 23 on both sides of the substrate 20, a NiCr-Au conductor is vapor-deposited, a resist film obtained by the same method as above is formed on this, and KI+I 2 +H 2 O etching solution
At the same time, a conductor pattern is formed by etching the Ni--Cr using an etching solution of Hcl+H 2 O (FIG. 2f). Then, SiO 2 −
The thermal head is completed by depositing a Ta 2 O 5 protective film 25 on the surface of the resistor 23 (FIG. 2g).
以上の如くして製作されたサーマルヘツドの抵
抗値のばらつきは±10％程度であり、平面上に発
熱体を形成した場合と同程度であり、充分な加工
精度が得られた。 The variation in resistance value of the thermal head manufactured as described above was about ±10%, which was about the same as when the heating element was formed on a flat surface, and sufficient processing accuracy was obtained.
本発明の加工法を採用することによつて、密着
型イメージセンササーマルヘツド等のハイブリツ
ト素子の小型化を図ることができる。 By employing the processing method of the present invention, it is possible to downsize hybrid elements such as a contact type image sensor thermal head.
以上発明した通り、本発明のフオトリソエツチ
ング加工法によれば、被エツチング物に貼着する
フオトレジストは平滑なステージ上に載置した状
態で露光されているので、マスクパターンが精度
良く再現される。さらに、精度の良いパターンが
形成されたフイルムレジストを基板に貼着した
後、現像、エツチングを施しているので、基板の
極面部分に於ても精度の高いフオトエツチング加
工が行える。
As described above, according to the photolithography processing method of the present invention, the photoresist attached to the object to be etched is exposed while being placed on a smooth stage, so that the mask pattern can be reproduced with high accuracy. Ru. Furthermore, since the film resist on which a highly accurate pattern is formed is adhered to the substrate and then developed and etched, highly accurate photoetching can be performed even on the extreme surface of the substrate.
第１図ａ，ｂ，ｃ，ｄ，ｅ，ｆは本発明方法の
実施工程を示す説明図、第２図ａ，ｂ，ｃ，ｄ，
ｅ，ｆ，ｇは本発明を適用したサーマルヘツドの
製作工程を示す説明図、第３図は曲面を有する基
板に対する従来のフオトエツチング加工法の説明
図。
符号の説明、１……ステージ、２……フイル
ム、３……ホトマスク、４……光源、５……レジ
スト、６……導体薄膜、１０……基板、１５……
ドライフイルムレジスト。
Figure 1 a, b, c, d, e, f is an explanatory diagram showing the implementation steps of the method of the present invention, Figure 2 a, b, c, d,
e, f, and g are explanatory diagrams showing the manufacturing process of a thermal head to which the present invention is applied, and FIG. 3 is an explanatory diagram of a conventional photoetching processing method for a substrate having a curved surface. Explanation of symbols, 1...Stage, 2...Film, 3...Photomask, 4...Light source, 5...Resist, 6...Conductor thin film, 10...Substrate, 15...
Dry film resist.
Claims (1)
基板に貼着してエツチングを行うフオトリソエツ
チング加工法であつて、 平滑なステージ上に載置したドライフイルムレ
ジストを露光して、フイルム上に所望のパターン
のレジストを形成するレジスト露光工程と、 このレジストを有するドライフイルムレジスト
をステージから移動してレジスト面を貼着対象と
する曲面を有する基板に貼着する貼着工程と、 レジスト上のフイルムを剥離した後、レジスト
を現像し、次いでこの現像したレジストをマスク
としてエツチング処理を施し、曲面部分を含む基
板に所望のパターンの導体薄膜をエツチングする
現像、エツチング工程とを有することを特徴とす
る曲面を有する基板のフオトリソエツチング加工
法。[Claims] 1. A photolithographic etching process in which a film-like photoresist is attached to a curved substrate and etched, comprising: exposing a dry film resist placed on a smooth stage; a resist exposure step of forming a resist with a desired pattern on the film; a pasting step of moving the dry film resist having the resist from a stage and pasting the resist surface onto a substrate having a curved surface to be pasted; After peeling off the film on the resist, the resist is developed, and then an etching process is performed using the developed resist as a mask to etch a conductive thin film in a desired pattern on a substrate including curved portions. A photolithography processing method for a substrate having a curved surface characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22118885A JPS6280281A (en) | 1985-10-04 | 1985-10-04 | Photolithoetching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22118885A JPS6280281A (en) | 1985-10-04 | 1985-10-04 | Photolithoetching method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6280281A JPS6280281A (en) | 1987-04-13 |
| JPH0520515B2 true JPH0520515B2 (en) | 1993-03-19 |
Family
ID=16762854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22118885A Granted JPS6280281A (en) | 1985-10-04 | 1985-10-04 | Photolithoetching method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6280281A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103313520B (en) * | 2012-03-14 | 2016-07-06 | 深圳光启创新技术有限公司 | The manufacture method of a kind of Curved surface metal figure and Curved surface metal image substrate |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5916433A (en) * | 1982-07-20 | 1984-01-27 | Matsushita Electric Ind Co Ltd | Selective calling receiver |
-
1985
- 1985-10-04 JP JP22118885A patent/JPS6280281A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5916433A (en) * | 1982-07-20 | 1984-01-27 | Matsushita Electric Ind Co Ltd | Selective calling receiver |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6280281A (en) | 1987-04-13 |
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