JPS61184654A - デ−タ受信監視装置 - Google Patents

デ−タ受信監視装置

Info

Publication number
JPS61184654A
JPS61184654A JP60025622A JP2562285A JPS61184654A JP S61184654 A JPS61184654 A JP S61184654A JP 60025622 A JP60025622 A JP 60025622A JP 2562285 A JP2562285 A JP 2562285A JP S61184654 A JPS61184654 A JP S61184654A
Authority
JP
Japan
Prior art keywords
data
reception
register
flag
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60025622A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0433064B2 (enExample
Inventor
Masao Komatsu
小松　政夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60025622A priority Critical patent/JPS61184654A/ja
Publication of JPS61184654A publication Critical patent/JPS61184654A/ja
Publication of JPH0433064B2 publication Critical patent/JPH0433064B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Communication Control (AREA)
JP60025622A 1985-02-13 1985-02-13 デ−タ受信監視装置 Granted JPS61184654A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60025622A JPS61184654A (ja) 1985-02-13 1985-02-13 デ−タ受信監視装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60025622A JPS61184654A (ja) 1985-02-13 1985-02-13 デ−タ受信監視装置

Publications (2)

Publication Number Publication Date
JPS61184654A true JPS61184654A (ja) 1986-08-18
JPH0433064B2 JPH0433064B2 (enExample) 1992-06-02

Family

ID=12170974

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60025622A Granted JPS61184654A (ja) 1985-02-13 1985-02-13 デ−タ受信監視装置

Country Status (1)

Country Link
JP (1) JPS61184654A (enExample)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58155036U (ja) * 1982-04-07 1983-10-17 オムロン株式会社 直列デ−タ伝送制御装置
JPS5923659A (ja) * 1982-07-29 1984-02-07 Sharp Corp デ−タ伝送制御装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58155036U (ja) * 1982-04-07 1983-10-17 オムロン株式会社 直列デ−タ伝送制御装置
JPS5923659A (ja) * 1982-07-29 1984-02-07 Sharp Corp デ−タ伝送制御装置

Also Published As

Publication number Publication date
JPH0433064B2 (enExample) 1992-06-02

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