JPS61183579U - - Google Patents

Info

Publication number
JPS61183579U
JPS61183579U JP6691085U JP6691085U JPS61183579U JP S61183579 U JPS61183579 U JP S61183579U JP 6691085 U JP6691085 U JP 6691085U JP 6691085 U JP6691085 U JP 6691085U JP S61183579 U JPS61183579 U JP S61183579U
Authority
JP
Japan
Prior art keywords
stud
layer
circuit
erected
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6691085U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6691085U priority Critical patent/JPS61183579U/ja
Publication of JPS61183579U publication Critical patent/JPS61183579U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案多層回路基板の断面図、第2
図はこの考案の効果を確認するための試験例の説
明図、第3図は従来の基板の断面図である。 1,11……第1層回路、2,12……スルー
スタツド、3,13……第2層回路、4,14…
…絶縁層、5,15……基板。
Figure 1 is a cross-sectional view of this invented multilayer circuit board, Figure 2
The figure is an explanatory diagram of a test example for confirming the effect of this invention, and FIG. 3 is a sectional view of a conventional board. 1,11...First layer circuit, 2,12...Through stud, 3,13...Second layer circuit, 4,14...
...Insulating layer, 5,15...Substrate.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 絶縁基板上に第1層回路及び絶縁層を介して所
望数の2層以上の回路を多層に有し、各回路層間
を導通用スルースタツドにて導通する多層回路基
板において、前記スルースタツド立設部の上記回
路の一部を予め除去し、該除去部にスルースタツ
ドを立設したことを特徴とする多層回路基板。
In a multilayer circuit board that has a first layer circuit and a desired number of two or more layers of circuits via an insulating layer on an insulating substrate, and conducts between each circuit layer with a through stud for continuity, the through stud is erected. 1. A multilayer circuit board, characterized in that a part of the above-mentioned circuit is removed in advance, and a through stud is erected in the removed part.
JP6691085U 1985-05-08 1985-05-08 Pending JPS61183579U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6691085U JPS61183579U (en) 1985-05-08 1985-05-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6691085U JPS61183579U (en) 1985-05-08 1985-05-08

Publications (1)

Publication Number Publication Date
JPS61183579U true JPS61183579U (en) 1986-11-15

Family

ID=30600241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6691085U Pending JPS61183579U (en) 1985-05-08 1985-05-08

Country Status (1)

Country Link
JP (1) JPS61183579U (en)

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