JPS61183577U - - Google Patents
Info
- Publication number
- JPS61183577U JPS61183577U JP6684285U JP6684285U JPS61183577U JP S61183577 U JPS61183577 U JP S61183577U JP 6684285 U JP6684285 U JP 6684285U JP 6684285 U JP6684285 U JP 6684285U JP S61183577 U JPS61183577 U JP S61183577U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor package
- circuit board
- printed circuit
- conductive pattern
- electrode piece
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 claims description 2
- 239000000853 adhesive Substances 0.000 claims 1
- 230000001070 adhesive effect Effects 0.000 claims 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
第１図は本考案実施例の導電パターンを示す平
面図、第２図ａ〜ｃは本考案実施例のプリント基
板を用いて半導体パツケージを固着する工程を説
明する断面図、第３図は従来における半導体パツ
ケージの固着状態を示す断面図、第４図は従来に
おける半導体パツケージの装着方法の一例を説明
するための分解斜視図、第５図は本考案に用いら
れるに適した半導体パツケージの一例を示す斜視
図、第６図は第５図に示す半導体パツケージを従
来のプリント基板上に固定した状態を示す断面図
である。
１……プリント基板、２……導電パターン、３
……半導体パツケージ、４……電極片、５……半
田、９……スリツト。
FIG. 1 is a plan view showing a conductive pattern according to an embodiment of the present invention, FIGS. 4 is an exploded perspective view illustrating an example of a conventional mounting method for a semiconductor package, and FIG. 5 is an example of a semiconductor package suitable for use in the present invention. FIG. 6 is a sectional view showing the semiconductor package shown in FIG. 5 fixed on a conventional printed circuit board. 1... Printed circuit board, 2... Conductive pattern, 3
...Semiconductor package, 4...Electrode piece, 5...Solder, 9...Slit.
Claims (1)
ツケージから導出した電極片を半田の如き導電性
接着剤にて固定するようにしたプリント基板にお
いて、前記導電パターンに、半導体パツケージの
電極片の先端を挿入するスリツトを形成したこと
を特徴とするプリント基板。 In a printed circuit board in which an electrode piece led out from a semiconductor package is fixed onto a printed conductive pattern using a conductive adhesive such as solder, a slit is provided for inserting the tip of the electrode piece of the semiconductor package into the conductive pattern. A printed circuit board characterized by forming.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6684285U JPS61183577U (en) | 1985-05-08 | 1985-05-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6684285U JPS61183577U (en) | 1985-05-08 | 1985-05-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61183577U true JPS61183577U (en) | 1986-11-15 |
Family
ID=30600114
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6684285U Pending JPS61183577U (en) | 1985-05-08 | 1985-05-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61183577U (en) |
-
1985
- 1985-05-08 JP JP6684285U patent/JPS61183577U/ja active Pending