JPS61177734A - Hybrid ic - Google Patents

Hybrid ic

Info

Publication number
JPS61177734A
JPS61177734A JP60018168A JP1816885A JPS61177734A JP S61177734 A JPS61177734 A JP S61177734A JP 60018168 A JP60018168 A JP 60018168A JP 1816885 A JP1816885 A JP 1816885A JP S61177734 A JPS61177734 A JP S61177734A
Authority
JP
Japan
Prior art keywords
pellet
glass epoxy
capacitors
epoxy substrate
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60018168A
Other languages
Japanese (ja)
Inventor
Masahide Murakami
村上　正秀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60018168A priority Critical patent/JPS61177734A/en
Publication of JPS61177734A publication Critical patent/JPS61177734A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
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    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/19011—Structure including integrated passive components
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To enable miniaturization by reducing the mounting area more than mounting chip capacitors and chip resistors, by a method wherein a pellet with capacitors and resistors formed on an Si wafer out of thin films is mounted on a glass epoxy substrate. CONSTITUTION:A pellet 1 with capacitors and resistors formed on an Si wafer out of thin films is mounted on the glass epoxy substrate 2 with an adhesive 3. Next, the pads of th capacitor-resistor pellet 1 are connected to conductor patterns 4 on the substrate 2 with Au wires 5 by wire bonding.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明に、ガラスエポキシ基板上に半導体ベレット、チ
ップコンデンサ、チップ抵抗等の部品が搭載されて形成
される混成集積回路において小形化、高′４ＦＩｔ度化
を計る技術に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to miniaturization and high-performance hybrid integrated circuits formed by mounting components such as semiconductor pellets, chip capacitors, and chip resistors on a glass epoxy substrate. Concerning technology to measure 4FIT degree.

〔従来の技術〕[Conventional technology]

従来、ガラスエポキシ基板上に半導体ペレット。 Conventionally, semiconductor pellets are placed on a glass epoxy substrate.

チップコンデンサ、チップ抵抗等の部品が搭載されて混
成集積回路が形成されていた。Components such as chip capacitors and chip resistors were mounted to form hybrid integrated circuits.

〔発明が解決しＬうとする問題点〕[Problems that the invention attempts to solve]

上述した従来の混成集積回路では、チップコンデンサ、
チップ抵抗の実装面積が大きい為、小形化には不適であ
り、又、高ｆ＃度で温度係数の等しいコンデンサ、抵抗
ｔ−実現するのは困難であるという欠点がある。The conventional hybrid integrated circuit described above uses chip capacitors,
Since the mounting area of the chip resistor is large, it is not suitable for miniaturization, and it also has the drawback that it is difficult to realize a capacitor and a resistor with equal temperature coefficients at high f# degrees.

〔問題点を解決するための手段〕[Means for solving problems]

シリコンウェハー上に薄膜を便ってコンデンサ及び抵抗
を形成したペレットヲガラスエボキシ基板上に搭載し、
上記コンデンサ及び抵抗が形成されたペレットのパッド
と、上記ガラスエポキシ基板上の導体パターンとをワイ
ヤボンディング法にて、Ａｕワイヤで接続を行う。Capacitors and resistors are formed by forming a thin film on a silicon wafer, and the pellets are mounted on a glass epoxy substrate.
The pad of the pellet on which the capacitor and resistor are formed is connected to the conductor pattern on the glass epoxy substrate by a wire bonding method using an Au wire.

〔実施例〕〔Example〕

＠１図は本発明の一実施例の部分平面図で、第２図は、
第１図のＸ−Ｙにおける断面図である。@Figure 1 is a partial plan view of an embodiment of the present invention, and Figure 2 is a partial plan view of an embodiment of the present invention.
FIG. 2 is a sectional view taken along line XY in FIG. 1;

シリコンウェハー上に薄膜を便ってコンデンサ及び抵抗
を形成したペレット１をガラスエポキシ基板２に接着剤
３でマウントする。A pellet 1 in which a capacitor and a resistor are formed by forming a thin film on a silicon wafer is mounted on a glass epoxy substrate 2 with an adhesive 3.

次に、コンデンサ及び抵抗ペレット１のパッドとガラス
エポキシ基板２上の導体パターン４とをワイヤボンディ
ング法にて、Ａｕワイヤ５で接続を行う。Next, the pads of the capacitor and resistor pellet 1 and the conductor pattern 4 on the glass epoxy substrate 2 are connected using the Au wire 5 by wire bonding.

〔発明の効果〕〔Effect of the invention〕

以上説明した工うに本発明に、シリコンウェハー上に薄
膜を使ってコンデンサ及び抵抗を形成し几ペレットヲガ
ラスエボキシ基板上に搭載することにエリ、チップコン
デンサ、チップ抵抗全搭載するエリも実装面積が小さく
なり、小形化が可能になる。又、半導体ペレットが搭載
されるような混成集積回路においてに、半導体ペレット
と同じ工程にて搭載することができる為、製造工程の短
縮にもなる。その他、薄膜にてコンデンサ及び抵抗を形
成するので高精度で温度係数が等しいコンデンサ、抵抗
の実現が可能である。As explained above, in the present invention, a capacitor and a resistor are formed using a thin film on a silicon wafer, and the chip capacitor and a chip resistor are mounted on a glass epoxy substrate. It becomes smaller and can be miniaturized. Further, in a hybrid integrated circuit in which a semiconductor pellet is mounted, the semiconductor pellet can be mounted in the same process as the semiconductor pellet, thereby shortening the manufacturing process. In addition, since capacitors and resistors are formed using thin films, it is possible to realize capacitors and resistors with high precision and equal temperature coefficients.

【図面の簡単な説明】[Brief explanation of the drawing]

１１図は本発明の一実施例を示す部分平面図で。 第２図にそのＸ−Ｙにおける断面図である。 １・・・・・・コンデンサ及び抵抗が形成されたペレッ
ト、２・・・・・・ガラスエポキシ基板、３・・・・・
・接着剤、４・・・・・・導体パターン、５・・・・・
・Ａｕワイヤ。FIG. 11 is a partial plan view showing one embodiment of the present invention. FIG. 2 is a sectional view taken along the line X-Y. 1... Pellet on which capacitors and resistors are formed, 2... Glass epoxy substrate, 3...
・Adhesive, 4... Conductor pattern, 5...
・Au wire.

Claims (1)

【特許請求の範囲】[Claims] 　シリコンウェハー上に薄膜を使ってコンデンサ及び抵
抗を形成したペレットをガラスエポキシ基板上に搭載し
、前記コンデンサ及び抵抗が形成されたペレットのパッ
ドと、前記ガラスエポキシ基板上の導体パターンとをワ
イヤボンディング法にて、Ａｕワイヤで接続を行つたこ
とを特徴とする混成集積回路。A pellet in which a capacitor and a resistor are formed using a thin film on a silicon wafer is mounted on a glass epoxy substrate, and the pad of the pellet on which the capacitor and resistor is formed is connected to a conductor pattern on the glass epoxy substrate using a wire bonding method. A hybrid integrated circuit characterized in that connections are made using Au wires.
JP60018168A 1985-02-01 1985-02-01 Hybrid ic Pending JPS61177734A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60018168A JPS61177734A (en) 1985-02-01 1985-02-01 Hybrid ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60018168A JPS61177734A (en) 1985-02-01 1985-02-01 Hybrid ic

Publications (1)

Publication Number Publication Date
JPS61177734A true JPS61177734A (en) 1986-08-09

Family

ID=11964077

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60018168A Pending JPS61177734A (en) 1985-02-01 1985-02-01 Hybrid ic

Country Status (1)

Country Link
JP (1) JPS61177734A (en)

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