JPS60144965A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPS60144965A
JPS60144965A JP59000616A JP61684A JPS60144965A JP S60144965 A JPS60144965 A JP S60144965A JP 59000616 A JP59000616 A JP 59000616A JP 61684 A JP61684 A JP 61684A JP S60144965 A JPS60144965 A JP S60144965A
Authority
JP
Japan
Prior art keywords
resistor
substrate
hybrid integrated
integrated circuit
glass epoxy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59000616A
Other languages
Japanese (ja)
Inventor
Masahide Murakami
村上　正秀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59000616A priority Critical patent/JPS60144965A/en
Publication of JPS60144965A publication Critical patent/JPS60144965A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/19011—Structure including integrated passive components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To trim a function by loading a resistance pattern formed on an insulating substrate on a glass epoxy substrate, to which a circuit pattern is shaped, and wire-bonding the resistance pattern and the circuit pattern. CONSTITUTION:A resistance pattern 2 is formed on a ceramic substrate 1 and a resistor is shaped previously. The resistor is mounted on a glass epoxy substrate 3 to which a circuit pattern is formed. The resistor and the circuit pattern on the substrate 3 are connected by wires 5 through a wire bonding method. A function can be trimmed in a hybrid integrated circuit manufactured in this manner.

Description

【発明の詳細な説明】 本発明は、混成集積回路に関し、特にガラスエ。[Detailed description of the invention] TECHNICAL FIELD The present invention relates to hybrid integrated circuits, and in particular to glass chips.

ボキシ基板上に半導体ベレット、チップコンデンサ、チ
ップ抵抗等の部品が搭載されて形成された、混成集積回
路に関する。The present invention relates to a hybrid integrated circuit formed by mounting components such as a semiconductor bullet, a chip capacitor, and a chip resistor on a boxy substrate.

従来、ガ２スエボキシ基板にて形成される混成集積回路
は、半導体ベット、チップコンデンサ、チップ抵抗等が
上記ガラスエポキシ基板上に搭載されて形成されている
。′しかし抵抗体としては通常チップ抵抗を使用してい
る為、機能トリミングが必要な回路は形成できないとい
う欠点がめった。Conventionally, a hybrid integrated circuit formed using a glass epoxy substrate is formed by mounting a semiconductor bed, a chip capacitor, a chip resistor, etc. on the glass epoxy substrate. 'However, since chip resistors are usually used as resistors, they often have the disadvantage that circuits that require functional trimming cannot be formed.

本発明の目的は、上記機能トリミングが可能な混成集積
回路を提供することにのる。An object of the present invention is to provide a hybrid integrated circuit capable of the above-mentioned functional trimming.

不発明の特徴は、セラミック基板などの絶縁基板上に、
薄膜又は厚膜で形成された抵抗パターンを上記ガラスエ
ポキシ基板上に搭載し、ワイヤボンディング法によって
上記抵抗パターンとガラスエポキシ基板上の回路パター
ンとを接続することに工って形成される混成集積回路ｖ
ｃめる。The inventive feature is that on an insulating substrate such as a ceramic substrate,
A hybrid integrated circuit formed by mounting a resistor pattern formed of a thin film or a thick film on the glass epoxy substrate, and connecting the resistor pattern and the circuit pattern on the glass epoxy substrate using a wire bonding method. v
c.meru.

本発明によれば、上記ガラスエポキシ基板上に搭載され
た薄膜又は厚膜で形成された抵抗を電気的特性を測定し
ながらトリミングすることにより、機能トリミングが可
能となる。又、相対精度が必要な抵抗も従来のチップ抵
抗では不可能でめったが上記方法でセラミック基板等の
絶縁基板上前記相対精度の抵抗を薄膜又は厚膜で形成し
てガラスエポキシ基板上に搭載することが可能となる。According to the present invention, functional trimming is possible by trimming a resistor formed of a thin film or a thick film mounted on the glass epoxy substrate while measuring its electrical characteristics. In addition, resistors that require relative accuracy are rarely possible with conventional chip resistors, but the above method can be used to form a resistor with the relative accuracy as a thin or thick film on an insulating substrate such as a ceramic substrate, and then mount it on a glass epoxy substrate. becomes possible.

次に本発明の一実施例について説明する。Next, one embodiment of the present invention will be described.

第１図は本実飾物の混成集積回路の部分平面図。FIG. 1 is a partial plan view of the hybrid integrated circuit of this actual ornament.

第２図は第１図のＸ−ＹｔｔＣｓｐける断面図でめる。FIG. 2 is a sectional view taken along the line X-YttCsp in FIG.

先ず１図のように、上２ミック基板ｌ上に、薄膜で抵抗
パターン２を形成して抵抗体全作って置く。次に回路パ
ターンが形成されたガラスエポキシ基板３上に前記抵抗
体を接着剤４でマワントし前記抵抗体とガラスエポキシ
基板３上の回路パターンをワイヤボンディング法に工っ
てワイヤ５で接続する。First, as shown in Fig. 1, a resistor pattern 2 is formed with a thin film on the upper 2-micro board 1 to fabricate the entire resistor. Next, the resistor is mounted on the glass epoxy substrate 3 on which the circuit pattern is formed using an adhesive 4, and the resistor and the circuit pattern on the glass epoxy substrate 3 are connected by wire bonding using a wire 5.

以上のようＶｒ−製造された混成集積回路は、機能トリ
ミングが可能となる。The Vr-manufactured hybrid integrated circuit as described above can be functionally trimmed.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示す部分平面図で、第２図
はそのＸ−Ｙにおける断面図である。FIG. 1 is a partial plan view showing one embodiment of the present invention, and FIG. 2 is a sectional view taken along the line X-Y.

Claims (1)

【特許請求の範囲】 絶縁基板上に形成された抵抗パターンをガラスエポキシ
基板上に搭載し、ワイヤボンディング法″。 によって前記抵抗パターンとガラスエポキシ基板上の回
路パターンとｔ−接続したことを特徴とする混成集積回
路。[Claims] A resistor pattern formed on an insulating substrate is mounted on a glass epoxy substrate, and the resistor pattern is T-connected to a circuit pattern on the glass epoxy substrate by a wire bonding method. hybrid integrated circuit.
JP59000616A 1984-01-06 1984-01-06 Hybrid integrated circuit Pending JPS60144965A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59000616A JPS60144965A (en) 1984-01-06 1984-01-06 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59000616A JPS60144965A (en) 1984-01-06 1984-01-06 Hybrid integrated circuit

Publications (1)

Publication Number Publication Date
JPS60144965A true JPS60144965A (en) 1985-07-31

Family

ID=11478660

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59000616A Pending JPS60144965A (en) 1984-01-06 1984-01-06 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS60144965A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60202983A (en) * 1984-03-28 1985-10-14 松下電器産業株式会社 Integrated circuit
US10099459B2 (en) 2013-11-27 2018-10-16 Henkel IP & Holding GmbH Adhesive for insulative articles

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60202983A (en) * 1984-03-28 1985-10-14 松下電器産業株式会社 Integrated circuit
US10099459B2 (en) 2013-11-27 2018-10-16 Henkel IP & Holding GmbH Adhesive for insulative articles

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