JPH03211763A - Hybrid integrated circuit - Google Patents

Hybrid integrated circuit

Info

Publication number
JPH03211763A
JPH03211763A JP755690A JP755690A JPH03211763A JP H03211763 A JPH03211763 A JP H03211763A JP 755690 A JP755690 A JP 755690A JP 755690 A JP755690 A JP 755690A JP H03211763 A JPH03211763 A JP H03211763A
Authority
JP
Japan
Prior art keywords
cavity
paste
bare chip
hybrid integrated
pellet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP755690A
Other languages
Japanese (ja)
Other versions
JP3071438B2 (en
Inventor
Kazuharu Ishihama
石濱　和治
Yoshiro Tabata
田畑　義郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KOZAN DENKI KOGYO KK
NEC Corp
Original Assignee
KOZAN DENKI KOGYO KK
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by KOZAN DENKI KOGYO KK, NEC Corp filed Critical KOZAN DENKI KOGYO KK
Priority to JP2007556A priority Critical patent/JP3071438B2/en
Publication of JPH03211763A publication Critical patent/JPH03211763A/en
Application granted granted Critical
Publication of JP3071438B2 publication Critical patent/JP3071438B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

PURPOSE:In a hybrid IC where bare chips are mounted, to mount a bare chip on another side too thereby promoting high density, high integration, and miniaturization by providing a cavity at one side of a board so as to bury a bare chip in the cavity. CONSTITUTION:A pellet 7 is mounted with Ag paste in the cavity of an insulating substrate 9 having said cavity at one side, and is bonded with a gold wire 8, and then precoat resin 6 is poured in the cavity. But care shall be taken so that it may no protrude. After completion of the mounting, bonding, and precoating works at the side where the cavity exists, a pellet 7 is mounted with Ag paste similarly on the side without cavity, and is bonded. After application of precoating resin 6, printing is done with solder pate 5 on the side where the cavity exists, and a miniflat 1, a chip capacitor 2, and a minimold are mounted. After mounting discrete parts on the side where the cavity exists, printing is done similarly with a solder paste 5, and a miniflat 1, a chip capacitor 2, and a minimold are mounted.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、混成集積回路に関し、特に絶縁基板上にベア
チップ搭載する構成をもつ混成集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit, and particularly to a hybrid integrated circuit having a configuration in which a bare chip is mounted on an insulating substrate.

〔従来の技術〕[Conventional technology]

近年、装置の小型化への要求から回路の集積が大幅に進
められてきており集積規模が大きくなるにつれＩＣで補
えきれない回路が多く発生する。In recent years, the integration of circuits has been greatly advanced due to the demand for miniaturization of devices, and as the scale of integration increases, many circuits that cannot be replaced by ICs are generated.

そのためＩＣの補助回路として混成集積回路がますます
必要性１重要性を増してくる。混成集積回路は、絶縁基
板（例えばセラミック基板）上に導体膜、抵抗膜などを
形成し能動素子であるＩＣ。Therefore, the necessity and importance of hybrid integrated circuits as auxiliary circuits for ICs is increasing. A hybrid integrated circuit is an IC that is an active element and has a conductive film, a resistive film, etc. formed on an insulating substrate (for example, a ceramic substrate).

トランジスタ、タイオード類、および受動素子であるコ
ンデンサ、コイル、抵抗を搭載し種々の回路機能をもた
せ通信装置、コンピュータ用中央処理装置など数多くの
分野に応用されている。従来の混成集積回路は、絶縁基
板上にＩＣをディスクリート部品あるいはペレット品で
搭載し、受動素子である抵抗およびコンデンサは厚膜・
薄膜で形成しあるいはチップ部品で搭載する。Equipped with transistors, diodes, and passive elements such as capacitors, coils, and resistors, they provide various circuit functions and are used in many fields such as communication devices and central processing units for computers. In conventional hybrid integrated circuits, ICs are mounted as discrete components or pellet products on an insulating substrate, and passive elements such as resistors and capacitors are mounted using thick films.
It is formed with a thin film or mounted with a chip component.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の混成集積回路は、ディスクリート部品を
ベアチップ部品にかえて搭載することにより４Ａ積化し
たが、ベアチップは、片面搭載しかできず片面は、すべ
てディスクリート部品になるため、基板占有面積が大き
くなり小型化の妨げになる。又、ベアチップ搭載面にデ
ィスクリート部品を搭載する時は、ベアチップ保護コー
ティングの凹凸があるため半田印刷ができないなどの欠
点がある。The conventional hybrid integrated circuit described above achieved 4A integration by replacing discrete components with bare chip components, but bare chips can only be mounted on one side, and one side is all discrete components, so it occupies a large board area. This will hinder miniaturization. Furthermore, when discrete components are mounted on the bare chip mounting surface, there are drawbacks such as the inability to perform solder printing due to the unevenness of the bare chip protective coating.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、ベアチップ搭載の混成集積回路において、基
板片面にくぼみを設けペレットをそのくぼみに埋めこみ
、かつもう一方の而にベアチップ搭載することを特徴と
する。The present invention is characterized in that, in a hybrid integrated circuit mounted with a bare chip, a recess is provided on one side of the substrate, a pellet is buried in the recess, and the bare chip is mounted on the other side.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は、本発明の一実施例の士、面図であり、第２図
は、本発明の一実施例の断面図である。片面に本発明に
よるくぼみをもった絶縁基板０のくぼみに、ベレット７
をＡｇペースト４でマウントを行い金線８でボンディン
グしてプリコート樹脂６をくぼみに流し込む、ただし、
はみださないよう注意する。くぼみのある面のマウント
、ボンディング、プリコート作業完了後にくぼみのない
面のベレット７を同様にＡｇペースト４でマウントしボ
ンディングを行う。プリコート樹脂６塗布後くぼみのあ
る面に半田ペースト５にて印刷を行い、ミニフラット１
．チップコンデンサ２．ミニモールド３を搭載する。く
ぼみのある面にディスクリート部品を搭載後にくぼみの
ない面を半田ペースト５を同様に半田印刷してミニフラ
ット１．チップコンデンサ２．ミニモールド３を搭載す
る。FIG. 1 is a plan view of one embodiment of the present invention, and FIG. 2 is a sectional view of one embodiment of the present invention. A pellet 7 is placed in the recess of an insulating substrate 0 having a recess according to the present invention on one side.
Mount with Ag paste 4, bond with gold wire 8, and pour precoat resin 6 into the recess, however,
Be careful not to let it stick out. After completing the mounting, bonding, and precoating work on the surface with the depression, the bullet 7 on the surface without the depression is similarly mounted with Ag paste 4 and bonded. After applying pre-coat resin 6, print on the concave surface with solder paste 5, and create mini flat 1.
．． Chip capacitor 2. Equipped with Mini Mold 3. After mounting the discrete component on the surface with the recess, print solder paste 5 on the surface without the recess in the same manner as mini-flat 1. Chip capacitor 2. Equipped with Mini Mold 3.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ベアチップ搭載のバイブ
ワットＩＣで基板片面にくぼみを設けてベアチップをそ
のくぼみに埋めこむことにより、もう一方の面もベアチ
ップ搭載ができ、それによって高密度化、高集積化、小
型化できる効果がある。As explained above, the present invention enables the bare chip to be mounted on the other side by providing a recess on one side of the substrate and embedding the bare chip in the recess in the VibeWatt IC mounted with a bare chip, thereby achieving high density and high performance. It has the effect of integration and miniaturization.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の上面図、第２図は本発明の
一実施例の断面図である。 １・・・ミニフラット、２・・・チップコンデンサ、３
・・・ミニモールド、４・・・Ａｌｌペースト、５・・
・半田ペースト、６・・・プリコート樹脂、７・・・ベ
レット、８・・・金線、 ９・・・絶縁基板。FIG. 1 is a top view of one embodiment of the present invention, and FIG. 2 is a sectional view of one embodiment of the present invention. 1...Mini flat, 2...Chip capacitor, 3
...Mini mold, 4...All paste, 5...
・Solder paste, 6... Precoat resin, 7... Bellet, 8... Gold wire, 9... Insulating board.

Claims (1)

【特許請求の範囲】[Claims] 　ベアチップ搭載の混成集積回路において、基板片面に
くぼみを設けペレットをそのくぼみに埋めこみ、かつも
う一方の面もベアチップ搭載する構造を有することを特
徴とする混成集積回路。A hybrid integrated circuit mounted with a bare chip, characterized in that it has a structure in which a recess is provided on one side of the substrate, a pellet is embedded in the recess, and a bare chip is mounted on the other side as well.
JP2007556A 1990-01-16 1990-01-16 Hybrid integrated circuit Expired - Fee Related JP3071438B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007556A JP3071438B2 (en) 1990-01-16 1990-01-16 Hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007556A JP3071438B2 (en) 1990-01-16 1990-01-16 Hybrid integrated circuit

Publications (2)

Publication Number Publication Date
JPH03211763A true JPH03211763A (en) 1991-09-17
JP3071438B2 JP3071438B2 (en) 2000-07-31

Family

ID=11669075

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007556A Expired - Fee Related JP3071438B2 (en) 1990-01-16 1990-01-16 Hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JP3071438B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5795799A (en) * 1995-05-31 1998-08-18 Nec Corporation Method for manufacturing electronic apparatus sealed by concave molded resin enveloper

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5828889A (en) * 1981-08-14 1983-02-19 株式会社日立製作所 Hybrid integrated circuit board
JPS6428855A (en) * 1987-07-23 1989-01-31 Nec Corp Package for semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5828889A (en) * 1981-08-14 1983-02-19 株式会社日立製作所 Hybrid integrated circuit board
JPS6428855A (en) * 1987-07-23 1989-01-31 Nec Corp Package for semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5795799A (en) * 1995-05-31 1998-08-18 Nec Corporation Method for manufacturing electronic apparatus sealed by concave molded resin enveloper

Also Published As

Publication number Publication date
JP3071438B2 (en) 2000-07-31

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