JPS62219532A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS62219532A JPS62219532A JP61063476A JP6347686A JPS62219532A JP S62219532 A JPS62219532 A JP S62219532A JP 61063476 A JP61063476 A JP 61063476A JP 6347686 A JP6347686 A JP 6347686A JP S62219532 A JPS62219532 A JP S62219532A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- frame
- integrated circuit
- circuit device
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 239000011347 resin Substances 0.000 claims abstract description 17
- 229920005989 resin Polymers 0.000 claims abstract description 17
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000000465 moulding Methods 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 6
- 229910000679 solder Inorganic materials 0.000 abstract description 5
- 238000007747 plating Methods 0.000 abstract description 3
- 238000007598 dipping method Methods 0.000 abstract description 2
- 230000010354 integration Effects 0.000 abstract description 2
- 238000005476 soldering Methods 0.000 abstract description 2
- 238000005259 measurement Methods 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、小型化と構成の簡略化を図った半導体集積
回路装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device that is miniaturized and has a simplified configuration.
第４図は従来のＩＣに外付部品を接続した半導体集積回
路装置の平面図で、この例では、ＩＣおよび外付部品を
基板にマウントし、基板上の配線でＩＣと外付部品を接
続したものを示している。Figure 4 is a plan view of a conventional semiconductor integrated circuit device in which external parts are connected to an IC. In this example, the IC and external parts are mounted on a board, and the IC and external parts are connected by wiring on the board. It shows what was done.
すなわち、第４図において、１は樹脂モール□ドパッケ
ージで、ＩＣチップ（図示せず）が樹脂モールドされて
いる。４ａは前記ＩＣチップの入出力ピン、４ｂは外付
部品６と接続する接続ピン、４ＣはＧＮＤピン、７は基
板、８ａは前記ＩＣチップの入出力配線、８ｂは前記Ｉ
Ｃチップと外付部品６を接続する配線、８Ｃは基板表面
のＧＮＤ配線、９は前記基板７の表と裏を接続するスル
ーホール、１０は基板裏面のＧＮＤ配線を示している。That is, in FIG. 4, 1 is a resin molded package, and an IC chip (not shown) is molded with resin. 4a is an input/output pin of the IC chip, 4b is a connection pin to be connected to the external component 6, 4C is a GND pin, 7 is a board, 8a is an input/output wiring of the IC chip, 8b is a connection pin for connecting to the external component 6
Wiring connecting the C chip and the external component 6, 8C is a GND wiring on the front surface of the substrate, 9 is a through hole connecting the front and back sides of the substrate 7, and 10 is a GND wiring on the back side of the substrate.
従来、ＩＣチップに外付部品６を接続する場合は、第４
図に示、すように、基板７の上にＩＣチップと外付部品
６をマウントし、基板７上にプリントされた配線８ｂに
よって、ＩＣチップの接続ピン４ｂと外付部品６とを接
続し、一方をＧＮＤ配線８ｃによってＧＮＤピン４ｃと
接続する。この場合、基板表面の配線だけでは、他の入
出力配線８ａと交差する場合があり、第４図に示したよ
うにスルーホール９と基板裏面のＧＮＤ配線１０を用い
てジャンプ配線を行う場合がある。Conventionally, when connecting the external component 6 to the IC chip, the fourth
As shown in the figure, the IC chip and the external component 6 are mounted on the board 7, and the connecting pins 4b of the IC chip and the external component 6 are connected by the wiring 8b printed on the board 7. , one side is connected to the GND pin 4c by a GND wiring 8c. In this case, the wiring on the front surface of the board may intersect with other input/output wiring 8a, and jump wiring may be performed using the through hole 9 and the GND wiring 10 on the back of the board as shown in FIG. be.
また外付部品６の周辺のリーク発生防止や耐湿性向上の
ために、部品を樹脂コーティングする場合がある。Further, in order to prevent leakage around the external component 6 and improve moisture resistance, the component may be coated with a resin.
上記のように構成された従来の半導体集積回路装置では
、基板７」−にＩＣチップと外付部品６をマウントし、
基板７上の配線でこれを接続しているために、ＩＣチッ
プと外信部品６およびその配線のための面積が必要とな
り、平面的に非常に大きな面積が必要となるという欠点
があった。In the conventional semiconductor integrated circuit device configured as described above, an IC chip and external components 6 are mounted on a substrate 7''.
Since these are connected by wiring on the substrate 7, an area is required for the IC chip, the foreign communication component 6, and the wiring thereof, and there is a drawback that a very large area is required in terms of plane.
また基板７」二の配線を２層もしくはそれ以上にする必
要が生じ、基板コストが非常に」二がるとともに、外付
部品６の樹脂コーティングなどで工程数が増加するとい
う欠点があった。In addition, it becomes necessary to have two or more layers of wiring on the board 7'2, resulting in a significant decrease in board cost and an increase in the number of steps required for resin coating of external parts 6, etc.
この発明は、」二記のような問題点を解消するためにな
されたもので、小型で、かつ工程数を減少せしめた半導
体集積回路装置を得ることを目的とする。This invention has been made to solve the problems mentioned in item 2 above, and aims to provide a semiconductor integrated circuit device that is small in size and has a reduced number of manufacturing steps.
Ｃ問題点を解決するための手段〕
この発明に係る半導体集積回路装置は、ＩＣチップがグ
イポンドされ、ＩＣチップと所定のピンとの間にワイヤ
ボンドが施されたフレームと、ＩＣチップの外付部品が
マウントされ、この外付部品と所定のピンとが接続され
たフレームとを背中合せにはり付け、ＩＣチップと外信
部品とを同一の樹脂モールドに封入し、さらに背中合せ
にされたピン同士を電気的に接続したものである。Means for Solving Problem C] A semiconductor integrated circuit device according to the present invention includes a frame on which an IC chip is mounted and wire bonded between the IC chip and predetermined pins, and external parts of the IC chip. is mounted, and a frame to which this external component and predetermined pins are connected are glued back to back, the IC chip and the foreign component are encapsulated in the same resin mold, and the pins that are back to back are electrically connected to each other. It is connected to.
この発明においては、ＩＣチ・ンプと外付部品をそれぞ
れ独立してマウントした２つのフレームを背中合わせに
固定して、同一樹脂モールドにて封入することにより、
外形寸法が小さくなるとともに、外部配線も省略でき、
さらにモールド樹脂内に封入された各部品の信頼性も向
上する。In this invention, two frames in which an IC chip and external components are mounted independently are fixed back to back and encapsulated in the same resin mold.
The external dimensions are smaller and external wiring can be omitted.
Furthermore, the reliability of each component sealed within the mold resin is also improved.
第１図〜第３図はこの発明の一実施例を示すもので、第
１図は半導体集積回路装置の側断面図、第２図、第３図
は同じく」二面図と下面図をそれぞれ示す。1 to 3 show an embodiment of the present invention, in which FIG. 1 is a side sectional view of a semiconductor integrated circuit device, and FIGS. 2 and 3 are a top view and a bottom view, respectively. show.
これらの図において、第４図と同一符号は同一構成部分
を示し、］は樹脂モールドパッケージで、ＩＣチップ２
がフレーム３ａ上にグイポンドされ、ＩＣチップ２と接
続ピン４ｂとの間にポンディングワイヤ５によりワイヤ
ポンディングが施される。６は抵抗器、コンデンサ等の
外付部品で、フレーム３ｂＪ二にマウントされる。そし
て接続ピン４ｂと外付部品６とが接続され、両フレーム
３ａ、３ｂとを背中合せにはり付けて樹脂モールドした
後、背中合せにされた各ピン、すなわち、ＩＣチップ２
の入出力ピン４ａ、接続ピン４ｂ、ダイパッドと接続し
たＧＮＤピン４ｃとをメッキまたはハンダディップ等で
電気的に接続する。In these figures, the same reference numerals as in FIG. 4 indicate the same components, and ] indicates a resin mold package, and
is bonded onto the frame 3a, and wire bonding is performed with a bonding wire 5 between the IC chip 2 and the connection pin 4b. Reference numeral 6 indicates external components such as resistors and capacitors, which are mounted on the frame 3bJ2. Then, the connecting pin 4b and the external component 6 are connected, and after the frames 3a and 3b are glued back to back and resin molded, each pin placed back to back, that is, the IC chip 2
The input/output pin 4a, the connection pin 4b, and the GND pin 4c connected to the die pad are electrically connected by plating, solder dip, or the like.
この発明における半導体集積回路装置の製造過程におい
て、ＩＣチップ２をフレーム３ａにグイポンドし、ワイ
ヤボンドを完了するまでは、通常の集積回路装置の組立
てと同一のフローで行う。In the manufacturing process of the semiconductor integrated circuit device according to the present invention, the steps from mounting the IC chip 2 to the frame 3a to completing wire bonding are carried out in the same flow as for assembling a normal integrated circuit device.
一方、フレーム３ｂ上に外付部品６をマウントする方法
としては、ハンダリフロー等でハンダ付けを行う。On the other hand, as a method for mounting the external component 6 on the frame 3b, soldering is performed using solder reflow or the like.
この２種類のフレーム３ａ、３ｂを、モールド工程にお
いて、モールド金型上で位置決めピン（図示せず）を基
準にして、背中合わせに重ね合わせて、同一のモールド
樹脂にて封入し、ＩＣチップ２．フレーム３ａ、３ｂ、
外付部品６を固定する。In a molding process, these two types of frames 3a and 3b are stacked back to back on a mold with reference to positioning pins (not shown) and sealed with the same molding resin. Frames 3a, 3b,
Fix the external parts 6.
この状態では、２つのフレーム３ａ、３ｂおよび各ピン
４ａ、４ｂ、４ｃは機械的に接触しているだけであるの
で、接続不良を起す恐れがある。In this state, the two frames 3a, 3b and each pin 4a, 4b, 4c are only in mechanical contact, so there is a risk of a connection failure.
したがって、樹脂モールド後、メッキもしくはハンダデ
ィップ等の方法により、電気的に接続させる。したがっ
て、電気的に接続された各ピンは上面および下面の共通
のインタフェイスとなる。Therefore, after resin molding, electrical connections are made by plating, solder dipping, or the like. Therefore, each electrically connected pin provides a common interface for the top and bottom surfaces.
こうしてできた集積回路装置では、外付部品６の信頼性
も、ＩＣチップ２と同様の水準にまで高められる。In the integrated circuit device manufactured in this manner, the reliability of the external components 6 is also increased to the same level as that of the IC chip 2.
なお、上記実施例では、１つのＩＣチップ２と外付部品
６を同一パッケージに封入する場合について述べたが、
２つ以上のＩＣチップと、外付部品をマウントする場合
についても同様である。In addition, in the above embodiment, a case was described in which one IC chip 2 and external component 6 were enclosed in the same package.
The same applies to the case where two or more IC chips and external components are mounted.
さらに、ＩＣチップ２のワイヤボンドをバンプによって
作成する場合も同様である。Furthermore, the same applies when wire bonds of the IC chip 2 are created using bumps.
この発明は以」二説明したとおり、少なくとも１つのＩ
Ｃチップがグイポンドされ、このＩＣチップと所定のピ
ンとの間にワイヤボンドが施されたフレームと、ＩＣチ
ップの外付部品がマウントされ、この外付部品と所定の
ピンとが接続されたフレームとを背中合せにはり合せ、
ＩＣチップと外付部品とを同一の樹脂モールドに封入し
、さらに背中合せにされたピン同士を電気的に接続した
ので、各ピンが上面および下面の共通のインタフェイス
となり、したがって、集積度が高まり、小型化が図れる
とともに、外付部品を樹脂コーティングしなくても、信
頼性が高まるため、余分な工程を省略できる等の効果が
ある。As explained below, this invention provides at least one I.
A frame on which a C chip is mounted and wire bonded between this IC chip and a predetermined pin, and a frame on which an external component of the IC chip is mounted and this external component and a predetermined pin are connected. Glued back to back,
Since the IC chip and external components are encapsulated in the same resin mold, and the back-to-back pins are electrically connected, each pin serves as a common interface on the top and bottom surfaces, thus increasing the degree of integration. , it is possible to reduce the size and increase reliability without resin coating external parts, which has the effect of omitting extra steps.
第１図はこの発明の一実施例を示す半導体集積回路装置
の側断面図、第２図および第３図は第１図の上面図およ
び下面図、第４図は従来の半導体集積回路装置の上面図
を示す。
図において、１は樹脂モールドパッケージ、２はＩＣチ
ップ、３ａ、３ｂは７Ｌ／−ム、４ａは入出力ピン、４
ｂは接続ピン、４ＣはＧＮＤピン、５はポンディングワ
イヤ、６は外付部品である。
なお、各図中の同一符号は同一および相当部分を示す。
代理人 大 岩 増 雄 （ほか２名）第１図
第２図
白白白白白白白白白白
第３図
第４図FIG. 1 is a side sectional view of a semiconductor integrated circuit device showing an embodiment of the present invention, FIGS. 2 and 3 are top and bottom views of FIG. 1, and FIG. 4 is a side sectional view of a conventional semiconductor integrated circuit device. A top view is shown. In the figure, 1 is a resin mold package, 2 is an IC chip, 3a, 3b are 7L/-mu, 4a is an input/output pin, 4
b is a connection pin, 4C is a GND pin, 5 is a bonding wire, and 6 is an external component. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (and 2 others) Figure 1 Figure 2 White White White White White White White White Figure 3 Figure 4
Claims (1)
れ接続された半導体集積回路装置において、前記ＩＣチ
ップの少なくとも１つがダイボンドされ、前記ＩＣチッ
プと所定のピンとの間にワイヤボンドが施されたフレー
ムと、前記ＩＣチップの外付部品がマウントされ、この
外付部品と所定のピンとが接続されたフレームとを背中
合せにはり合せ、前記ＩＣチップと外付部品とを同一の
樹脂モールドに封入し、さらに背中合せにされたピン同
士を電気的に接続したことを特徴とする半導体集積回路
装置。In a semiconductor integrated circuit device in which external components such as resistors and capacitors are connected to IC chips, at least one of the IC chips is die-bonded, and a frame is provided with wire bonds between the IC chip and predetermined pins. and a frame on which the external parts of the IC chip are mounted and the external parts and predetermined pins are connected are glued back to back, and the IC chip and the external parts are encapsulated in the same resin mold, Furthermore, a semiconductor integrated circuit device is characterized in that pins placed back to back are electrically connected to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61063476A JPS62219532A (en) | 1986-03-19 | 1986-03-19 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61063476A JPS62219532A (en) | 1986-03-19 | 1986-03-19 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62219532A true JPS62219532A (en) | 1987-09-26 |
Family
ID=13230324
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61063476A Pending JPS62219532A (en) | 1986-03-19 | 1986-03-19 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62219532A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05211189A (en) * | 1992-01-28 | 1993-08-20 | Nec Corp | Semiconductor device and semiconductor chip |
-
1986
- 1986-03-19 JP JP61063476A patent/JPS62219532A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05211189A (en) * | 1992-01-28 | 1993-08-20 | Nec Corp | Semiconductor device and semiconductor chip |
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