JPS5828889A - Hybrid integrated circuit board - Google Patents
Hybrid integrated circuit boardInfo
- Publication number
- JPS5828889A JPS5828889A JP56126620A JP12662081A JPS5828889A JP S5828889 A JPS5828889 A JP S5828889A JP 56126620 A JP56126620 A JP 56126620A JP 12662081 A JP12662081 A JP 12662081A JP S5828889 A JPS5828889 A JP S5828889A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- integrated circuit
- circuit board
- hybrid integrated
- electronic components
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は混成集積回路基板に係わり、！Ｉ！ｊに高密度
集積回路に使用するに好適な混成集積回路基板に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hybrid integrated circuit board! I! The present invention relates to a hybrid integrated circuit board suitable for use in high-density integrated circuits.
従来の混成集積回路基板において、高密度に電子部品を
実装する一方法として、セラミック基板の両面に膜回路
を形成していた。しかし、該方法においても、電子部品
はセラミック基板の片面だけに実装］７ていた。このた
め、高密度に電子部品をセラミック基板に実装すること
が困離であるという欠点かを）つた。寸だ、セラミック
基板の両面に電子部品を搭載する場合においても、片面
に電子部品を接合する際の熱により、もう片面に実装さ
扛ている電子部品のロウ材が溶融して、当該面の電子部
品が脱＠、してし寸うという欠点があった。In conventional hybrid integrated circuit boards, film circuits have been formed on both sides of a ceramic substrate as a method for mounting electronic components at high density. However, even in this method, electronic components were mounted only on one side of the ceramic substrate. For this reason, the drawback is that it is difficult to mount electronic components on a ceramic substrate at high density. Even when electronic components are mounted on both sides of a ceramic substrate, the heat generated when the electronic components are bonded to one side melts the soldering material of the electronic components mounted on the other side, causing damage to that side. The drawback was that the electronic parts were easily removed.
本発明の目的は、高密度に電子部品を実装する方法とし
て、セラミック基板の両面に電子部品を接合し、かつ、
中ラミック基板をはさんで対向する部品を交互に配置す
ること、また、融点の異なる２種類のロウ材を用いるこ
とにより、セラミックノー：板の両面に電子部品を実装
した混成集積回路基板金・提供するにある。An object of the present invention is to bond electronic components to both sides of a ceramic substrate as a method for mounting electronic components at high density, and to
By alternately arranging opposing parts across a middle lamic board and using two types of brazing materials with different melting points, we are able to create a hybrid integrated circuit board with electronic components mounted on both sides of the board. It is on offer.
セラミック基板１には、チップコンデンサ３、フリップ
チップ素子２，２０、クリップビン４が搭載され１、該
電子部品はセラミック基板１の両面に塔載さ扛、かつ、
膜回路が形成さ扛ている。フリップチップ素ｒ２に、Ｉ
ハンダ５に、１、すｊ膜回路に接合さ扛、ハンダ５に共
晶・・ンダを１１いている。ゴた、フリップチップ
膜回路に接合さ扛、ハンダ６に高７！ｌ’ｌｌハング介
・用いている。フリップチップ素子２とフリップデツプ
素子２０（弓、、セラミック基板１不一に１、さＸ７て
゛、父ｆ７１に配置さ．？′１、、前記フリップチップ
素−ｒ同志が前記セラミック基板をはさんでχ・］向し
７だ配置にならないように配置さ；ｊしている。すでに
、膜回路に接合 。A chip capacitor 3, flip chip elements 2, 20, and a clip bin 4 are mounted on the ceramic substrate 1, and the electronic components are mounted on both sides of the ceramic substrate 1, and
A membrane circuit is formed. On the flip chip element r2, I
To the solder 5, 1 is bonded to the film circuit, and to the solder 5 is 11 eutectic... solder. Got it, bonded to the flip chip membrane circuit, solder 6 to 7! l'll be using it for hanging. Flip-chip element 2 and flip-deep element 20 (Arranged on ceramic substrate 1, unevenly 1, x7, father f71.?'1, The flip-chip element-r comrades sandwich the ceramic substrate. χ・] It is arranged so that it is not in a 7-sided arrangement; it is already connected to the membrane circuit.
さ和，た−７リツブヂツプ累ｒ−のハンダ６ｋｌ約３０
。Sawa, T-7 Rib-zips 6kl of solder approx. 30
.
Ｃで溶酸１１する。フリッブヂノフ”二な，了２を１と
合するハフ ｐ− ５ （ｄ約１８Ｏｎで溶融するので
、ハンダ５を溶量中する際の熱釦、ハンダ６ケ竹ＩＡ’
ｌ！ してし１うほどの熱で（ｄない。また、ハンダ５
を・溶融する際の熱がハンダ６に直接、伝搬（７ないよ
うに、中ラミック基板１をはさんで、フリップチップ素
子２。Dissolve acid with C. Hribuddinov ``2, Combine 2 with 1 Hough p- 5 (D It melts at about 18 On, so when melting the solder 5, press the hot button, solder 6 pieces IA'
l! The heat is so high that it will scorch.
・Place the flip-chip element 2 between the middle ramic substrates 1 to prevent the heat from melting from directly propagating to the solder 6 (7).
２０紹交１１−に配置さ扛ている。It is placed in 20 introductions and 11-.
本発明の一実が１ｉ例にょ；７１−ば、電子）耶品ケレ
ラミツク基板の両面に搭載することができるのーｃｚ
／１１１，、成果積回路の高密度実装が１叶能となる効
果がある。One of the fruits of the present invention is that it can be mounted on both sides of the electronic circuit board.
/111, has the effect of making high-density packaging of product circuits possible.
本発明によ扛げ、電子部品をセラミック基板の両面に搭
載することができるので、混成集積回路の茜密度実装が
「げ能となる効果がある。According to the present invention, electronic components can be mounted on both sides of a ceramic substrate, which has the effect of increasing the density of mounting of hybrid integrated circuits.
第１［ツ比１、従来技術を説明する概略図、第２図（ｄ
：従来技術の説明図、第３図し１：本発明の一実が１ｊ
例を説明する鳥１敵図、第４図Ｃ本発明の詳細な説明図
である。
１・・セラミック基板、２・・・フリップチップ素子、
第１図
第２図
第３図
メ
茅 ４図Figure 1 (ratio 1, schematic diagram explaining the prior art, Figure 2 (d)
: Explanatory diagram of the prior art, Figure 3. 1: A fruit of the present invention is 1j
FIG. 4C is a detailed explanatory diagram of the present invention. 1...ceramic substrate, 2...flip chip element,
Figure 1 Figure 2 Figure 3 Mekaya Figure 4
Claims (1)
ック基板の両面に形成さ扛た膜回路、前記十ラミック基
板の両面にロウ接合さ、ｆｌ、た電子部品から成る混成
集積回路基板において、前記セラミック基板の両面に接
合さｆｌ、る電子部品を、前記セラミック基板をはさん
で互いに交互に配置したことｋ ′ｌ！ｌ’徴とする混
成集積回路基板。 ２、特許請求の範囲第１項において、前記十ラミック基
板に電子ｔｒｌＩＳ品を接合するロウ旧として融点の異
なる２種類のロウ利をセラミック基板の片面ずつに用い
たことを特徴とする混成集積回路基板。[Claims] 1° At least a ceramic substrate; 1) a hybrid film circuit formed on both sides of the ceramic substrate; In the integrated circuit board, the electronic components bonded to both sides of the ceramic substrate are alternately arranged with the ceramic substrate in between. A hybrid integrated circuit board having l' characteristics. 2. The hybrid integrated circuit according to claim 1, characterized in that two types of soldering materials having different melting points are used on each side of the ceramic substrate as the soldering material for bonding the electronic trlIS product to the ceramic substrate. substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56126620A JPS5828889A (en) | 1981-08-14 | 1981-08-14 | Hybrid integrated circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56126620A JPS5828889A (en) | 1981-08-14 | 1981-08-14 | Hybrid integrated circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5828889A true JPS5828889A (en) | 1983-02-19 |
Family
ID=14939701
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56126620A Pending JPS5828889A (en) | 1981-08-14 | 1981-08-14 | Hybrid integrated circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5828889A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03211763A (en) * | 1990-01-16 | 1991-09-17 | Nec Corp | Hybrid integrated circuit |
| JPH05235261A (en) * | 1992-02-20 | 1993-09-10 | Nec Corp | Surface-mounting type hybrid integrated circuit device |
| JP2008235369A (en) * | 2007-03-16 | 2008-10-02 | Fujitsu Ltd | Semiconductor device |
-
1981
- 1981-08-14 JP JP56126620A patent/JPS5828889A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03211763A (en) * | 1990-01-16 | 1991-09-17 | Nec Corp | Hybrid integrated circuit |
| JPH05235261A (en) * | 1992-02-20 | 1993-09-10 | Nec Corp | Surface-mounting type hybrid integrated circuit device |
| JP2008235369A (en) * | 2007-03-16 | 2008-10-02 | Fujitsu Ltd | Semiconductor device |
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