JPH0373589A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPH0373589A JPH0373589A JP21034589A JP21034589A JPH0373589A JP H0373589 A JPH0373589 A JP H0373589A JP 21034589 A JP21034589 A JP 21034589A JP 21034589 A JP21034589 A JP 21034589A JP H0373589 A JPH0373589 A JP H0373589A
- Authority
- JP
- Japan
- Prior art keywords
- component
- paste
- hybrid integrated
- hole
- soldered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims abstract description 6
- 229920005989 resin Polymers 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 14
- 239000000919 ceramic Substances 0.000 abstract description 8
- 239000004020 conductor Substances 0.000 abstract description 5
- 229910000679 solder Inorganic materials 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 4
- 239000003990 capacitor Substances 0.000 abstract description 3
- 238000007598 dipping method Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract description 2
- 239000010409 thin film Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 5
- 230000010354 integration Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
Landscapes
- Combinations Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、混成集積回路に関し、特に高周波特性を必要
とする混成集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit, and particularly to a hybrid integrated circuit that requires high frequency characteristics.
近年、装置の小型化への要求から回路の集積度が大幅に
増大し、それに合わせてIC(集積回路)の集積度が増
してきた。しかし、ICの集積度が増す以上に小型化が
要求され、ICだけでは達成できない回路、特性が多く
みられる。そのため、ICの周辺回路を含んだ混成集積
回路の必要性1重要性が増してくる。混成集積回路は、
絶縁基板、たとえばセラミック基板、プリント基板など
の導体膜、厚膜抵抗、あるいは薄膜抵抗を形成する。更
に、その上に能動素子であるIC,)ランジスタ、ダイ
オード類および受動素子を搭載し、種々の回路機能をも
たせた複合機能を有し、通信装置、コンピュータなどの
高信頼性の産業用から家電製品やゲームなどの民生用ま
であらゆる電気部品の小型化に寄与している。In recent years, the degree of integration of circuits has increased significantly due to the demand for miniaturization of devices, and the degree of integration of ICs (integrated circuits) has increased accordingly. However, as the degree of integration of ICs increases, miniaturization is required, and there are many circuits and characteristics that cannot be achieved with ICs alone. Therefore, the need for hybrid integrated circuits including peripheral circuits of ICs is increasing in importance. Hybrid integrated circuits are
A conductive film, thick film resistor, or thin film resistor is formed on an insulating substrate, such as a ceramic substrate or a printed circuit board. Furthermore, active elements such as ICs, transistors, diodes, and passive elements are mounted on top of it, and it has a complex function that provides various circuit functions, making it suitable for use in everything from highly reliable industrial applications such as communication devices and computers to home appliances. It is contributing to the miniaturization of all kinds of electrical components, including products and consumer products such as games.
従来の混成集積回路は、セラミック基板上に配線パター
ンを配し、集積度を増すために第1層の上に絶縁ガラス
を設けて第2層の導体パターンを形成するという2層構
造の基板となる。Conventional hybrid integrated circuits have a two-layer structure in which a wiring pattern is placed on a ceramic substrate, and insulating glass is provided on the first layer to form a second layer of conductor patterns to increase the degree of integration. Become.
上述した従来の混成集積回路用の基板は、高集積度を図
るために2層構造をなしており、第1I!10回路パタ
ーンと第2層の回路パターンを絶縁ガラス(約40μm
)で分離する構造のため、高周波領域において、第1層
と第2層の信号が混ざるという(クロストーク)現象が
おこる。一方、高周波特性を必要とする回路用の基板と
して、多層基板を利用し、内層に全面のグランド電位の
パターンを配し、シールド効果をもたせる!戒もあるが
非常に高価なものとなり、低価格化の障害となっている
。The conventional substrate for hybrid integrated circuits described above has a two-layer structure in order to achieve a high degree of integration. The 10 circuit patterns and the second layer circuit pattern are made of insulating glass (approximately 40 μm
), a phenomenon (crosstalk) occurs in which the signals of the first layer and the second layer are mixed in the high frequency region. On the other hand, a multilayer board is used as a board for circuits that require high frequency characteristics, and a ground potential pattern is placed on the entire surface of the inner layer to provide a shielding effect! Although there are precepts, they are very expensive and are an obstacle to lower prices.
本発明の混成集積回路は、グランド電位の導体パターン
部に裏1表が導通しているスルーホールを有する絶縁基
板2枚に片面のみ部品搭載し、部品搭載されていない面
どうしを背中合せではりつける構造を有している。The hybrid integrated circuit of the present invention has a structure in which components are mounted on only one side of two insulating substrates each having a through hole whose back side is electrically connected to a conductor pattern section at ground potential, and the surfaces on which no components are mounted are attached back to back. have.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は、本発明の一実施例の一部断面図である。FIG. 1 is a partial sectional view of an embodiment of the present invention.
スルーホール1を有するセラミック基板2で、スルーホ
ールを通して電気的に導通させるべく、導電性厚膜ベー
ス)(Ag/Pc1l系)で導体3を印刷する。そのセ
ラミック基板2上にICベアチップ4をポンディング法
で搭載し、更にコンデンサ5.抵抗などの受動部品を半
田リフロー法で半田接続し、部品搭載を完了させる。同
様に、もう−枚セラミック基板に部品を搭載する。これ
ら2枚の基板の部品を搭載していない面にそれぞれ導電
性樹脂のAgペースト6を約40mμの厚さで塗布し、
第2図に示すようにAgペーストを塗布した面どうしを
重ね合せて120℃で熱硬化させる0次に、外部端子を
挿入し、半田浸せき法で半田接続をする。On a ceramic substrate 2 having a through hole 1, a conductor 3 is printed with a conductive thick film base (Ag/Pc11 system) to provide electrical continuity through the through hole. An IC bare chip 4 is mounted on the ceramic substrate 2 by a bonding method, and a capacitor 5. Passive components such as resistors are soldered using the solder reflow method to complete component mounting. Similarly, components are mounted on another ceramic substrate. Apply conductive resin Ag paste 6 to a thickness of about 40 mμ on each side of these two boards on which no components are mounted,
As shown in FIG. 2, the surfaces coated with Ag paste are placed one on top of the other and heat cured at 120° C. After that, external terminals are inserted and solder connections are made using the solder dipping method.
以上、説明したように本発明は、絶縁基板を背中合せに
2枚はり合わせ、貼り合せ材料を導電性樹脂とすること
により高周波特性においてクロストークを防ぐことがで
きる効果がある。また、従来の厚膜基板を使用すること
により安価な基板を利用できるという効果がある。As described above, the present invention has the effect of preventing crosstalk in high frequency characteristics by gluing two insulating substrates back to back and using conductive resin as the bonding material. Further, by using a conventional thick film substrate, an inexpensive substrate can be used.
第1図は本発明の一実施例に用いる基板の断面図、第2
図は本発明の一実施例を示す混成集積回路の断面図であ
る。
1・・・・・・スルーホール、2・・・・・・セラミッ
ク基板、3・・・・・・厚膜印刷導体、4・・・・・・
ICペアチップ、5・・・・・・コンデンサ、6・・・
・・・Agペースト、7・・・・・・ICベアチ、ブ保
護コート、8・・・・・・金ワイヤ−9・・・・・・フ
ラットバ、ケージIC。FIG. 1 is a cross-sectional view of a substrate used in one embodiment of the present invention, and FIG.
The figure is a sectional view of a hybrid integrated circuit showing one embodiment of the present invention. 1... Through hole, 2... Ceramic substrate, 3... Thick film printed conductor, 4...
IC pair chip, 5... Capacitor, 6...
...Ag paste, 7...IC bare base, protective coat, 8...gold wire 9...flat bar, cage IC.
Claims (1)
集積回路において、貼り合わせをする樹脂を導電性樹脂
とし、かつ、電位をグランド電位にすることを特徴とす
る混成集積回路。1. A hybrid integrated circuit having a configuration in which insulating substrates are bonded back to back, the bonding resin being a conductive resin and the potential being set to ground potential.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21034589A JPH0373589A (en) | 1989-08-14 | 1989-08-14 | Hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21034589A JPH0373589A (en) | 1989-08-14 | 1989-08-14 | Hybrid integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0373589A true JPH0373589A (en) | 1991-03-28 |
Family
ID=16587869
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21034589A Pending JPH0373589A (en) | 1989-08-14 | 1989-08-14 | Hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0373589A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08167457A (en) * | 1994-12-15 | 1996-06-25 | Kel Corp | Electrical connector |
-
1989
- 1989-08-14 JP JP21034589A patent/JPH0373589A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08167457A (en) * | 1994-12-15 | 1996-06-25 | Kel Corp | Electrical connector |
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