JPS6114531B2 - - Google Patents

Info

Publication number
JPS6114531B2
JPS6114531B2 JP56101082A JP10108281A JPS6114531B2 JP S6114531 B2 JPS6114531 B2 JP S6114531B2 JP 56101082 A JP56101082 A JP 56101082A JP 10108281 A JP10108281 A JP 10108281A JP S6114531 B2 JPS6114531 B2 JP S6114531B2
Authority
JP
Japan
Prior art keywords
register
output
clock pulse
flip
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56101082A
Other languages
English (en)
Japanese (ja)
Other versions
JPS582934A (ja
Inventor
Takashi Matsuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56101082A priority Critical patent/JPS582934A/ja
Publication of JPS582934A publication Critical patent/JPS582934A/ja
Publication of JPS6114531B2 publication Critical patent/JPS6114531B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Shift Register Type Memory (AREA)
  • Information Transfer Systems (AREA)
JP56101082A 1981-06-29 1981-06-29 デ−タ転送方式 Granted JPS582934A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56101082A JPS582934A (ja) 1981-06-29 1981-06-29 デ−タ転送方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56101082A JPS582934A (ja) 1981-06-29 1981-06-29 デ−タ転送方式

Publications (2)

Publication Number Publication Date
JPS582934A JPS582934A (ja) 1983-01-08
JPS6114531B2 true JPS6114531B2 (enrdf_load_stackoverflow) 1986-04-19

Family

ID=14291171

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56101082A Granted JPS582934A (ja) 1981-06-29 1981-06-29 デ−タ転送方式

Country Status (1)

Country Link
JP (1) JPS582934A (enrdf_load_stackoverflow)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0731656B2 (ja) * 1984-12-26 1995-04-10 株式会社日立製作所 非同期信号同期化回路
JPH08263435A (ja) * 1995-03-23 1996-10-11 Kofu Nippon Denki Kk 装置間データ転送回路

Also Published As

Publication number Publication date
JPS582934A (ja) 1983-01-08

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