JPS6114531B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer system between registers in which data is written using mutually asynchronous clock pulses.

Figure 1 is a block diagram of the conventional data transfer system, and Figure 2 is a time chart of the output uncertainty region, where A is the clock pulse CP1 and B is the register 1.
output Q ₁ , C represents the output Q ₂ of register 1, and D represents the clock pulse CP2.

In the figure, 1 and 2 are registers, CP1 and CP2 are mutually asynchronous clock pulses, DI ₁ to DI _o are parallel input signals, and DO ₁ to DO _o are parallel output signals.

In FIG. 1, parallel input signals DI ₁ to DI _o are written to register 1 using clock pulse CP1, and the output thereof is written to register 2 using clock pulse CP2 and transferred as parallel output signals DO ₁ to DO _o . Naturally, the period of clock pulse CP2 is clock pulse CP1.
All transfer methods are like this because the transfer will not take place unless the period is equal to or faster than the period of .
However, if DATAN is read at the rising edge of clock pulse CP1 as shown in Figure 2, the output of register 1
There is a time difference in the time for Q ₁ and Q ₂ to become DATAN due to variations in the elements in register 1. If clock pulse CP2 occurs at the time when this difference occurs and writes to register 2, the output _Q1 of register 1 will be
DATAN is written, but the output _Q2 of register 1 is
If you write DATAN-1, incorrect data will be written to register 2, and the parallel output signal DO ₁ ~
DO _o will be different from the parallel input signals DI ₁ to DI _o . Although the explanation has been made using two signals, if there are many signals, the time difference between the outputs of the register 1 described above will further increase, and erroneous signals will often occur. This is called the output skew, and this point is called the output uncertainty region. There is a drawback that the phenomenon described above occurs in the conventional transfer method.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer system that avoids the output uncertainty region of the previous stage register and writes data to the next stage in a stable region in order to eliminate the above-mentioned drawbacks, thereby allowing error-free data transfer.

In order to achieve the above object, the present invention provides flip-flops FF1 and FF1 for sample-holding a certain fixed level, corresponding to registers 1 and 2 driven by clock pulses CP1 and CP2 asynchronous to each other.
FF2 is provided, and the time when this fixed level is transferred to the output of flip-flop FF2 is regarded as a stable region, and data can be transferred without error by transferring data from register 1 to register 2 with the next clock pulse of clock pulse CP2. This is a data transfer method characterized by:

An embodiment of the present invention will be described below with reference to the drawings.

3 is a block diagram of a data transfer system according to an embodiment of the present invention, and FIG. 4 is a time chart in the case of FIG. 3. A to H correspond to points A to H in FIG. For the output of register 2, only one input is shown as a representative.

Components in the figure that have the same functions as those in FIG. 1 are indicated by the same symbols. 3 and 4 are NAND circuits with the same delay time, and FF1 and FF2 are D-type flip-flops. Input D of flip-flop FF1 is set at "H" level. clock pulse
CP1 and CP2 are asynchronous. As for operation, parallel data DI ₁ ~ generated by clock pulse CP1 system
At the same time as writing DI _o to register 1 using clock pulse CP1, write "H" level to flip-flop FF1, and use the output as data set completion signal No. 4.
Let's call it Figure B. This signal is clock pulse CP2
is inverted by the NAND circuit 3 and the clock pulse E in FIG. 4 is used to write the flip-flop FF2 to its output No.
Figure F is a data transfer permission signal. This signal and the clock pulse CP2 are NANDed by a NAND circuit 4 and used as a write clock for the register 2 and a reset signal for the flip-flop FF1 (FIG. 4G). As a result, it is possible to avoid an output uncertain region of the output data of register 1 and transfer data from register 1 to register 2 without error. That is, it is confirmed that the parallel input signal has been written to register 1 with the clock pulse CP2, and it is written to register 2 with the next clock, and the skew time of the output of register 1 is not as long as the interval between the cycles of clock pulse CP2. It is possible to avoid unstable areas and write in stable areas. Although this has been explained with a configuration using positive logic, it is also possible with a configuration using negative logic.

As explained in detail above, according to the present invention, when transferring parallel signals in a mutually asynchronous clock system, data can be transferred while avoiding the unstable region of the output of the register, so that data can be transferred without error. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional data transfer method, FIG. 2 is a time chart of the output uncertainty region in the case of FIG. 1, and FIG. 3 is a block diagram of a data transfer method according to an embodiment of the present invention. FIG. 4 is a time chart for the case of FIG. In the figure, 1 and 2 are registers, 3 and 4 are NAND circuits,
FF1, FF2 are flip-flops, CP1, CP2
is the clock pulse, DI ₁ to _{DI o} is the parallel input signal,
DO ₁ to _{DO o} are parallel output signals.

Claims (1)

[Claims] 1. A first register receives a parallel signal of 2 or more bits as input and is driven by a first clock pulse to sample and hold the input signal, a first flip-flop that holds a fixed level, and a second register driven by a second clock pulse. a second flip-flop that samples and holds the output of the first flip-flop;
A pulse obtained by ANDing the output of the second flip-flop and the second clock pulse is used as a write clock for the second register that samples and holds the output of the first register, and as a clear signal for the first flip-flop. Data transfer method.