SU1179318A1 - Device for rounding number - Google Patents

Abstract

A DEVICE FOR ROUNDING A NUMBER containing a standard word register and an additional word register, the information inputs of which are connected respectively to the first and second information inputs of the device, characterized in that, in order to improve the accuracy of rounding, it contains a counter, a decoder, an NL element and a delay element The output of which is connected to the inputs of the installation About the register of the standard word and the register of the additional word and the input of the resolution of the counter counter, the information input and output of which is Here, respectively, with the output of the register of the standard word and the output of the device, the input and output of the decoder are connected respectively to the output of the register of the additional word and the input of the NL element, the output of which is connected to the counting input of the counter, and the synchronous inputs of the standard word registers connected to the sync device.

Description

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The invention relates to computing technology and can be used in matching devices of automated information processing systems when creating integrated information systems. The aim of the invention is to improve the accuracy of rounding numbers. Figure 1 shows a diagram of a bit of correspondence of the agreed message formats, figure 2 shows a functional diagram of the device. The device contains the register 1 of the standard word, the register 2 is the additional word, the decoder 3, the element of the SRI 4, the counter 5, the delay element 6 and has a synchronous input 7, the first and upstream information inputs 8 and 9 and the output TO. The information input 8 of the device is connected to the information input of the register 1, the output of which is connected to the information input of the counter 5. The output of the counter 5 is connected to the output 10 of the device. Information input 9 of the device is connected to the information input of the register 2, the output of which is connected to the input of the decoder 3. The output of the third signal through the element OR 4 is connected to the counting input of the counter 5. The synchronous input 7 of the device is connected to the synchronous inputs of registers 1 and 2 and the input of element 6, output which is connected to the inputs of the installation About registers 1 and 2 and the enable input of the readout of the counter 5. The device operates as follows. The format message arrives on registers 1 and 2, and on register 1, the bit of which corresponds to format i), input (8) is written (Sk) of the most significant bits of the message format F, the remaining k bits of the message and (kp) information, are received at input 9 to register 2. On the contents of register 2 and decoder 3, a signal is generated; rounding, which, after passing through element 4, is added to the contents of register V on counter 5. From the output of counter 5 to output 10, a message is converted from format 1-2 to format P | . Consider the dynamics of the device. The older (6-lt) message bits of the Pg format on input 8 arrive at the input of register 1 and are remembered

there. The remaining k low-order bits at input 9 are entered into register 2. With the arrival of a clock signal at input 7, it enters the synchronous inputs of registers 1 and 2 and provides a rewriting of their contents, respectively, into counter 5 and decoder 3. Depending on the code value, arriving from register 2, a single signal appears at the strictly defined output of decoder 3. Only those outputs of decoder 3 are connected to the inputs of element 4, where a single signal appears when the 2 rounding code combinations are received from register 2. Allowed rounding code combinations are any code combinations in P most significant bits of register 2 that are service and should not affect the result of rounding, and well-defined code combinations in (kp) bits, defined in accordance with accepted rule of rounding When entering from register 2 the allowed rounding code combination to one of the outputs of decoder 3, which is connected to the input of element 4, there appears a single signal acting as a rounding signal. Passing element 4, this signal is fed to the counting input of counter 5, where it is summed up with the contents of register 1. Thus, the conversion of the message from the f-2 format, format g, is completed. The clock signal delayed by the element 6 at the time of forming the rounding signal and summing it with the contents of register 1 is fed to the resolution of reading the counters of counter 5, ensuring the result is read from the matching device to the output information processing system 10. The delayed clock signal is also fed to the O registers installation 1 and 2 and put them down, letting JJ take the most to the new rounding cycle. Resetting the contents of counter 5 is not good, because the contents of register 1 are entered into it in the & phase code code, the accuracy of message format conversion. (Rounded) It is possible to estimate the difference / ux / / X2-xJ, where 2 is the number X represented in the F format , 3 X, is the number X converted to the format F (. Let's compare cy1 to the size of the error &x; I for the well-known and proposed J-th device when converting the combination of N2 numbers represented in the format fj into the set of numbers X ,, presented in format F, (Tables 1 and 2). The format structure of the following: format p2 bit zero, first, from third to seventh (counting from the right) - informational, second service; format G, - all bits (from zero to quarter) - informational Results of the work of a known device when converting an aggregate of numbers into an aggregate X, are given in Table .1. The result of the operation of the proposed rounding device is given in Table 2. 18 The device for rounding the number Xg is five-bit. register 1, three-bit register 2, five-bit counter 5, a decoder 3 for three inputs, a delay element and an element OR 4 for two inputs. The fourth and eighth outputs of the decoder 3 are connected to the inputs of element 4. The single signal at these outputs is present when code combinations O 1 1 and 1 1 1 are on register 2, i.e. the following rounding rule is implemented: the rounding signal is aborted if the number recorded in the data bits of the rounding part of the format P message. more than half the value of the least significant bit of a FI message. Comparing the values of the PSUs in Tables 1 and 2, it can be concluded that in the proposed device the accuracy of rounding can be increased by 2-4 times in comparison with the known device for rounding.

10010000

10010001

10010010

1 O O 1 .0 O 1 1

10010100

10010101

10010110

10010111

Table 1

10010 1001 1 10011 10011 10011 10011 10011 10011

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table 2

Claims (1)

A DEVICE FOR NUMBER ROUND, containing a standard word register and an additional word register, the information inputs of which are connected respectively to the first and second information inputs of the device. characterized in that, in order to improve the accuracy of / 77 RSGZ / MDL # / rounding, it contains a counter, a descrambler, an OR element and a delay element, the output of which is connected to the inputs of the O setting of the standard word register and the additional word register and the counter enable input, the information input and output of which are connected respectively to the output of the standard word register and the device output, the input and output of the decoder are connected respectively to the output of the additional word register and the input of the OR element, the output of which is connected to the counter input of the counter, and the sync the standard word and the additional word and the input of the delay element are connected to the device sync input. SU .... 1179318