JPS582934A - デ−タ転送方式 - Google Patents
デ−タ転送方式Info
- Publication number
- JPS582934A JPS582934A JP56101082A JP10108281A JPS582934A JP S582934 A JPS582934 A JP S582934A JP 56101082 A JP56101082 A JP 56101082A JP 10108281 A JP10108281 A JP 10108281A JP S582934 A JPS582934 A JP S582934A
- Authority
- JP
- Japan
- Prior art keywords
- register
- output
- transfer method
- data transfer
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
- Shift Register Type Memory (AREA)
- Information Transfer Systems (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56101082A JPS582934A (ja) | 1981-06-29 | 1981-06-29 | デ−タ転送方式 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56101082A JPS582934A (ja) | 1981-06-29 | 1981-06-29 | デ−タ転送方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS582934A true JPS582934A (ja) | 1983-01-08 |
JPS6114531B2 JPS6114531B2 (enrdf_load_stackoverflow) | 1986-04-19 |
Family
ID=14291171
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56101082A Granted JPS582934A (ja) | 1981-06-29 | 1981-06-29 | デ−タ転送方式 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS582934A (enrdf_load_stackoverflow) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61151771A (ja) * | 1984-12-26 | 1986-07-10 | Hitachi Ltd | 非同期信号同期化回路 |
JPH08263435A (ja) * | 1995-03-23 | 1996-10-11 | Kofu Nippon Denki Kk | 装置間データ転送回路 |
-
1981
- 1981-06-29 JP JP56101082A patent/JPS582934A/ja active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61151771A (ja) * | 1984-12-26 | 1986-07-10 | Hitachi Ltd | 非同期信号同期化回路 |
JPH08263435A (ja) * | 1995-03-23 | 1996-10-11 | Kofu Nippon Denki Kk | 装置間データ転送回路 |
Also Published As
Publication number | Publication date |
---|---|
JPS6114531B2 (enrdf_load_stackoverflow) | 1986-04-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Valette | Analysis of Petri nets by stepwise refinements | |
JPS6378400A (ja) | Ram試験方式 | |
JPS62140072A (ja) | デジタル位相計回路 | |
JPS582934A (ja) | デ−タ転送方式 | |
CN113468095B (zh) | 高速串行传输数据相位对齐方法、存储介质及终端设备 | |
JPS6020200Y2 (ja) | 多トラツク記録装置用デ−タ信号デスキユ−化装置 | |
JP3071435B2 (ja) | 多ビット一致回路 | |
RU2046395C1 (ru) | Устройство управления | |
SU1265860A1 (ru) | Запоминающее устройство с самоконтролем | |
JP3285240B2 (ja) | 2ポートデータ保証の調停回路 | |
SU1056202A1 (ru) | Устройство дл контрол микропрограмм | |
SU1182534A1 (ru) | Устройство для сопряжения процессора с внешними абонентами | |
JP2924968B2 (ja) | 時間双方向シミュレーション装置 | |
SU1547076A1 (ru) | Преобразователь параллельного кода в последовательный | |
SU1183975A1 (ru) | Устройство дл сопр жени разноскоростных вычислительных устройств | |
Mishra | Some graph theoretic issues in vlsi design (algorithm, mos circuit) | |
JP2558802B2 (ja) | レジスタファイル | |
JPS6231427B2 (enrdf_load_stackoverflow) | ||
SU949657A1 (ru) | Микропрограммное управл ющее устройство | |
SU1487050A1 (ru) | Устройство доя контроля переходов | |
RU1789993C (ru) | Устройство дл редактировани элементов таблиц | |
Bunker et al. | Formal specification of the virtual component interface standard in the unified modeling language | |
SU1254487A1 (ru) | Устройство дл обнаружени конфликтов в процессоре | |
SU1177806A1 (ru) | Устройство для сопряжения ' цифровых измерительных приборов с цвм | |
SU1464294A1 (ru) | Устройство Нисневича дл контрол двоичной информации |