JPS61131869U - - Google Patents

Info

Publication number
JPS61131869U
JPS61131869U JP1476985U JP1476985U JPS61131869U JP S61131869 U JPS61131869 U JP S61131869U JP 1476985 U JP1476985 U JP 1476985U JP 1476985 U JP1476985 U JP 1476985U JP S61131869 U JPS61131869 U JP S61131869U
Authority
JP
Japan
Prior art keywords
chip element
substrate
integrated circuit
hybrid integrated
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1476985U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1476985U priority Critical patent/JPS61131869U/ja
Publication of JPS61131869U publication Critical patent/JPS61131869U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図aは、この考案の一実施例を示す混成集
積回路装置の要部概略斜視図、第1図bは、その
一部分の概略断面図、第2図aはこの考案の基板
加工の概念図、第2図bはこの考案の基板の概略
斜視図、第3図aは従来の混成集積回路装置を示
す要部概略斜視図、第3図bはその一部分の概略
断面図である。 図中、1は混成集積回路基板、2はチツプ取付
用電極、3はICチツプ、4は接続用導体パター
ン、5は接続用極細金属線、6は接着剤、7は基
板上の開孔部(角穴)である。なお、各図中同一
符号は同一または相当部分を示す。
FIG. 1a is a schematic perspective view of the main parts of a hybrid integrated circuit device showing an embodiment of this invention, FIG. 1b is a schematic sectional view of a part thereof, and FIG. 2a is a concept of substrate processing of this invention. 2B is a schematic perspective view of the substrate of this invention, FIG. 3A is a schematic perspective view of a main part of a conventional hybrid integrated circuit device, and FIG. 3B is a schematic sectional view of a portion thereof. In the figure, 1 is a hybrid integrated circuit board, 2 is an electrode for chip mounting, 3 is an IC chip, 4 is a conductive pattern for connection, 5 is a microfine metal wire for connection, 6 is an adhesive, and 7 is an opening on the board. (square hole). Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] セラミツク基板又は樹脂積層基板等の絶縁基板
を用い、その絶縁基板上にチツプ素子を搭載する
混成集積回路装置において、前記チツプ素子の取
付部分を孔設した基材と、前記孔設した基材と同
一寸法の基材により積層した前記絶縁基板を形成
し、この基板上に前記チツプ素子の取付用電極と
導体パターンを生成して、前記チツプ素子の電極
と前記導体パターン相互間を極細金属線を用いて
接続し、電子回路を構成したことを特徴とする混
成集積回路装置。
In a hybrid integrated circuit device in which an insulating substrate such as a ceramic substrate or a resin laminated substrate is used and a chip element is mounted on the insulating substrate, a base material in which a hole is formed for a mounting portion of the chip element, and a base material in which the hole is formed; The insulating substrate is formed by laminating base materials of the same size, electrodes and conductor patterns for mounting the chip element are formed on this substrate, and ultrafine metal wires are connected between the electrodes of the chip element and the conductor pattern. 1. A hybrid integrated circuit device characterized in that an electronic circuit is constructed by connecting the hybrid integrated circuit device using the following devices.
JP1476985U 1985-02-05 1985-02-05 Pending JPS61131869U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1476985U JPS61131869U (en) 1985-02-05 1985-02-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1476985U JPS61131869U (en) 1985-02-05 1985-02-05

Publications (1)

Publication Number Publication Date
JPS61131869U true JPS61131869U (en) 1986-08-18

Family

ID=30499997

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1476985U Pending JPS61131869U (en) 1985-02-05 1985-02-05

Country Status (1)

Country Link
JP (1) JPS61131869U (en)

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