JPS6433752U - - Google Patents
Info
- Publication number
- JPS6433752U JPS6433752U JP1987127769U JP12776987U JPS6433752U JP S6433752 U JPS6433752 U JP S6433752U JP 1987127769 U JP1987127769 U JP 1987127769U JP 12776987 U JP12776987 U JP 12776987U JP S6433752 U JPS6433752 U JP S6433752U
- Authority
- JP
- Japan
- Prior art keywords
- conductive pattern
- wiring board
- lead frame
- deposited
- feature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims 1
- 239000008188 pellet Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案に係る半導体装置の一実施例を
示す組立分解斜視図、第２図は第１図装置の組立
完了斜視図、第３図は第２図のＡ矢視図、第４図
及び第５図はそれぞれ本考案の他の実施例を示す
部分斜視図である。第６図はハイブリツドＩＣの
従来例を示す組立分解斜視図、第７図は第６図装
置の組立完了斜視図、第８図は第７図のＢ―Ｂ線
に沿う断面図である。
２０……リードフレーム、２１……一部（吊り
ピン）、２５……配線基板、２６……導電パター
ン、２７……電子部品。
FIG. 1 is an exploded perspective view showing an embodiment of the semiconductor device according to the present invention, FIG. 2 is a perspective view of the device shown in FIG. 1 after assembly, FIG. 5 and 5 are partial perspective views showing other embodiments of the present invention, respectively. FIG. 6 is an exploded perspective view showing a conventional example of a hybrid IC, FIG. 7 is a perspective view of the device shown in FIG. 6 after assembly, and FIG. 8 is a sectional view taken along line BB in FIG. 20... Lead frame, 21... Part (hanging pin), 25... Wiring board, 26... Conductive pattern, 27... Electronic component.
Claims (1)
パターン上に複数の半導体ペレツトを含む電子部
品をマウントした絶縁性の配線基板を、金属製リ
ードフレームの一部に直接的に橋架支持したこと
を特徴とする半導体装置。 A feature is that an insulating wiring board on which a conductive pattern is deposited and electronic components including a plurality of semiconductor pellets are mounted on the conductive pattern is directly bridge-supported on a part of the metal lead frame. semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987127769U JPH0735404Y2 (en) | 1987-08-21 | 1987-08-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987127769U JPH0735404Y2 (en) | 1987-08-21 | 1987-08-21 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6433752U true JPS6433752U (en) | 1989-03-02 |
| JPH0735404Y2 JPH0735404Y2 (en) | 1995-08-09 |
Family
ID=31380493
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987127769U Expired - Lifetime JPH0735404Y2 (en) | 1987-08-21 | 1987-08-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0735404Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61136249A (en) * | 1984-12-06 | 1986-06-24 | Nec Kansai Ltd | Hybrid ic |
-
1987
- 1987-08-21 JP JP1987127769U patent/JPH0735404Y2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61136249A (en) * | 1984-12-06 | 1986-06-24 | Nec Kansai Ltd | Hybrid ic |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0735404Y2 (en) | 1995-08-09 |