JPH0375536U - - Google Patents
Info
- Publication number
- JPH0375536U JPH0375536U JP13566089U JP13566089U JPH0375536U JP H0375536 U JPH0375536 U JP H0375536U JP 13566089 U JP13566089 U JP 13566089U JP 13566089 U JP13566089 U JP 13566089U JP H0375536 U JPH0375536 U JP H0375536U
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- integrated circuit
- hybrid integrated
- bare chip
- electronic components
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 1
Description
第１図は、本考案の一実施例における混成集積
回路基板を示す図であつて、ａは模式平面図、ｂ
は模式断面図である。第２図および第３図は、い
ずれも従来の混成集積回路基板を示す斜視図であ
つて、前者は回路基板全体を金属製ケースに収納
した状態を、後者は局部的に金属製ケースで電磁
遮へいした状態を示した図である。
符号の説明、１……金属製ケース、２……回路
基板、３……回路基板端子、４……ベア・チツプ
、５……ボンデイングワイヤ、６……絶縁性チツ
プコート、７……導電性樹脂、８……導体配線パ
ターン、９……絶縁性ガラス、１０……絶縁性ガ
ラスの窓。
FIG. 1 is a diagram showing a hybrid integrated circuit board according to an embodiment of the present invention, in which a is a schematic plan view and b is a schematic plan view.
is a schematic cross-sectional view. Figures 2 and 3 are both perspective views showing conventional hybrid integrated circuit boards. It is a diagram showing a shielded state. Explanation of symbols, 1... Metal case, 2... Circuit board, 3... Circuit board terminal, 4... Bare chip, 5... Bonding wire, 6... Insulating chip coat, 7... Conductive resin , 8... Conductor wiring pattern, 9... Insulating glass, 10... Insulating glass window.
Claims (1)
半導体電子部品を接続して構成された混成集積回
路であつて、前記半導体電子部品の少なくとも一
つがベア・チツプであり、該ベア・チツプ上に絶
縁性樹脂を被覆し、さらにその上を導電性樹脂で
覆い、かつ導電性樹脂を上記基板上のアース配線
に接続したことを特徴とする混成集積回路。 A hybrid integrated circuit configured by wiring a conductor on an insulating circuit board and connecting semiconductor electronic components to the wiring, wherein at least one of the semiconductor electronic components is a bare chip, and the bare chip What is claimed is: 1. A hybrid integrated circuit, comprising: covering an insulating resin thereon, further covering the top with a conductive resin, and connecting the conductive resin to a ground wiring on the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13566089U JPH0375536U (en) | 1989-11-22 | 1989-11-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13566089U JPH0375536U (en) | 1989-11-22 | 1989-11-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0375536U true JPH0375536U (en) | 1991-07-29 |
Family
ID=31682913
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13566089U Pending JPH0375536U (en) | 1989-11-22 | 1989-11-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0375536U (en) |
-
1989
- 1989-11-22 JP JP13566089U patent/JPH0375536U/ja active Pending
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