JPS61116448A - 同期回路 - Google Patents

同期回路

Info

Publication number
JPS61116448A
JPS61116448A JP59227019A JP22701984A JPS61116448A JP S61116448 A JPS61116448 A JP S61116448A JP 59227019 A JP59227019 A JP 59227019A JP 22701984 A JP22701984 A JP 22701984A JP S61116448 A JPS61116448 A JP S61116448A
Authority
JP
Japan
Prior art keywords
pulse
circuit
input
frame
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59227019A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0254982B2 (cg-RX-API-DMAC7.html
Inventor
Takashi Wakabayashi
隆 若林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59227019A priority Critical patent/JPS61116448A/ja
Publication of JPS61116448A publication Critical patent/JPS61116448A/ja
Publication of JPH0254982B2 publication Critical patent/JPH0254982B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/04Speed or phase control by synchronisation signals
    • H04L7/041Speed or phase control by synchronisation signals using special codes as synchronising signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP59227019A 1984-10-29 1984-10-29 同期回路 Granted JPS61116448A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59227019A JPS61116448A (ja) 1984-10-29 1984-10-29 同期回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59227019A JPS61116448A (ja) 1984-10-29 1984-10-29 同期回路

Publications (2)

Publication Number Publication Date
JPS61116448A true JPS61116448A (ja) 1986-06-03
JPH0254982B2 JPH0254982B2 (cg-RX-API-DMAC7.html) 1990-11-26

Family

ID=16854237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59227019A Granted JPS61116448A (ja) 1984-10-29 1984-10-29 同期回路

Country Status (1)

Country Link
JP (1) JPS61116448A (cg-RX-API-DMAC7.html)

Also Published As

Publication number Publication date
JPH0254982B2 (cg-RX-API-DMAC7.html) 1990-11-26

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