GB1432139A - Phase detector - Google Patents

Abstract

1432139 Phase comparators POST OFFICE 5 July 1973 [5 July 1972] 31430/72 Headings H3A and H3P A phase detector including two bi-stable circuits 20, 21 of the type which are switched by a clock input C to a state dependent on an applied data input D is characterized in that: the signal 22 whose phase is to be detected is applied to both C inputs; a reference signal 23 is applied to both D input; the signal 22 is delayed by a delay 25 and applied to a set input S of bi-stable 20 and a reset input R of bi-stable 21; and the outputs, Q, of the two bi-stables are summed in an adder R1, R2. Assume that bi-stables 20, 21 have been set and reset respectively, then the output at 24 on the application of the next C input will depend on the state of the signal at the D input at that time. If the reference signal 23 leads the signal 22 the D input is "1", and the application of the signal 22 sets both bi-stables to a "1" level, thus producing a "1" at output 24. Conversely if signal 22 leads the D input is still "0" when the C input is applied and both bi-stables are accordingly set to the "0" level to produce a "0" output at 24. If the two signals are co-incident, within a small tolerance range, the bi-stables remain in their existing states with a "1" level output from 20 and a "0" level output from 21. Output 24 is thus at an intermediate level. After the delay period determined by delay 25, both bi-stables are again switched to their initial states of "1" and "0" respectively. The detector is used in a retroactive control loop, for synchronizing a locally generated clock signal with a received data signal, Fig. 1 (not shown).