GB1432139A - Phase detector - Google Patents
Phase detectorInfo
- Publication number
- GB1432139A GB1432139A GB3143072A GB3143072A GB1432139A GB 1432139 A GB1432139 A GB 1432139A GB 3143072 A GB3143072 A GB 3143072A GB 3143072 A GB3143072 A GB 3143072A GB 1432139 A GB1432139 A GB 1432139A
- Authority
- GB
- United Kingdom
- Prior art keywords
- input
- signal
- stables
- output
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
1432139 Phase comparators POST OFFICE 5 July 1973 [5 July 1972] 31430/72 Headings H3A and H3P A phase detector including two bi-stable circuits 20, 21 of the type which are switched by a clock input C to a state dependent on an applied data input D is characterized in that: the signal 22 whose phase is to be detected is applied to both C inputs; a reference signal 23 is applied to both D input; the signal 22 is delayed by a delay 25 and applied to a set input S of bi-stable 20 and a reset input R of bi-stable 21; and the outputs, Q, of the two bi-stables are summed in an adder R1, R2. Assume that bi-stables 20, 21 have been set and reset respectively, then the output at 24 on the application of the next C input will depend on the state of the signal at the D input at that time. If the reference signal 23 leads the signal 22 the D input is "1", and the application of the signal 22 sets both bi-stables to a "1" level, thus producing a "1" at output 24. Conversely if signal 22 leads the D input is still "0" when the C input is applied and both bi-stables are accordingly set to the "0" level to produce a "0" output at 24. If the two signals are co-incident, within a small tolerance range, the bi-stables remain in their existing states with a "1" level output from 20 and a "0" level output from 21. Output 24 is thus at an intermediate level. After the delay period determined by delay 25, both bi-stables are again switched to their initial states of "1" and "0" respectively. The detector is used in a retroactive control loop, for synchronizing a locally generated clock signal with a received data signal, Fig. 1 (not shown).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB3143072A GB1432139A (en) | 1972-07-05 | 1972-07-05 | Phase detector |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB3143072A GB1432139A (en) | 1972-07-05 | 1972-07-05 | Phase detector |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1432139A true GB1432139A (en) | 1976-04-14 |
Family
ID=10322990
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB3143072A Expired GB1432139A (en) | 1972-07-05 | 1972-07-05 | Phase detector |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB1432139A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2119188A (en) * | 1982-04-28 | 1983-11-09 | Int Computers Ltd | Digital phase-locked loop |
GB2166611A (en) * | 1984-10-12 | 1986-05-08 | Schrack Elektronik Ag | Circuit for detecting asynchronism in alternating-voltage signals |
-
1972
- 1972-07-05 GB GB3143072A patent/GB1432139A/en not_active Expired
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2119188A (en) * | 1982-04-28 | 1983-11-09 | Int Computers Ltd | Digital phase-locked loop |
GB2166611A (en) * | 1984-10-12 | 1986-05-08 | Schrack Elektronik Ag | Circuit for detecting asynchronism in alternating-voltage signals |
GB2166611B (en) * | 1984-10-12 | 1989-03-01 | Schrack Elektronik Ag | Circuit arrangement for detecting deviations of the synchronism of at least two alternating-voltage signals |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
435 | Patent endorsed 'licences of right' on the date specified (sect. 35/1949) | ||
732 | Registration of transactions, instruments or events in the register (sect. 32/1977) | ||
PE20 | Patent expired after termination of 20 years |
Effective date: 19930704 |