JPS6088492A - 印刷配線板 - Google Patents

印刷配線板

Info

Publication number
JPS6088492A
JPS6088492A JP58196360A JP19636083A JPS6088492A JP S6088492 A JPS6088492 A JP S6088492A JP 58196360 A JP58196360 A JP 58196360A JP 19636083 A JP19636083 A JP 19636083A JP S6088492 A JPS6088492 A JP S6088492A
Authority
JP
Japan
Prior art keywords
resin layer
resin
printed
paste
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58196360A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0345909B2 (cg-RX-API-DMAC7.html
Inventor
瑛一 綱島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58196360A priority Critical patent/JPS6088492A/ja
Publication of JPS6088492A publication Critical patent/JPS6088492A/ja
Publication of JPH0345909B2 publication Critical patent/JPH0345909B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
JP58196360A 1983-10-20 1983-10-20 印刷配線板 Granted JPS6088492A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58196360A JPS6088492A (ja) 1983-10-20 1983-10-20 印刷配線板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58196360A JPS6088492A (ja) 1983-10-20 1983-10-20 印刷配線板

Publications (2)

Publication Number Publication Date
JPS6088492A true JPS6088492A (ja) 1985-05-18
JPH0345909B2 JPH0345909B2 (cg-RX-API-DMAC7.html) 1991-07-12

Family

ID=16356545

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58196360A Granted JPS6088492A (ja) 1983-10-20 1983-10-20 印刷配線板

Country Status (1)

Country Link
JP (1) JPS6088492A (cg-RX-API-DMAC7.html)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63265486A (ja) * 1987-04-23 1988-11-01 Matsushita Electric Ind Co Ltd 印刷配線板
JPH01241195A (ja) * 1988-03-23 1989-09-26 Matsushita Electric Ind Co Ltd 金属ベース印刷配線板
JPH0391989A (ja) * 1989-09-04 1991-04-17 Matsushita Electric Ind Co Ltd 金属基板

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63265486A (ja) * 1987-04-23 1988-11-01 Matsushita Electric Ind Co Ltd 印刷配線板
JPH01241195A (ja) * 1988-03-23 1989-09-26 Matsushita Electric Ind Co Ltd 金属ベース印刷配線板
JPH0391989A (ja) * 1989-09-04 1991-04-17 Matsushita Electric Ind Co Ltd 金属基板

Also Published As

Publication number Publication date
JPH0345909B2 (cg-RX-API-DMAC7.html) 1991-07-12

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