JPH0345909B2 - - Google Patents

Info

Publication number
JPH0345909B2
JPH0345909B2 JP19636083A JP19636083A JPH0345909B2 JP H0345909 B2 JPH0345909 B2 JP H0345909B2 JP 19636083 A JP19636083 A JP 19636083A JP 19636083 A JP19636083 A JP 19636083A JP H0345909 B2 JPH0345909 B2 JP H0345909B2
Authority
JP
Japan
Prior art keywords
resin layer
resin
printed
paste
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP19636083A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6088492A (ja
Inventor
Eiichi Tsunashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58196360A priority Critical patent/JPS6088492A/ja
Publication of JPS6088492A publication Critical patent/JPS6088492A/ja
Publication of JPH0345909B2 publication Critical patent/JPH0345909B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
JP58196360A 1983-10-20 1983-10-20 印刷配線板 Granted JPS6088492A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58196360A JPS6088492A (ja) 1983-10-20 1983-10-20 印刷配線板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58196360A JPS6088492A (ja) 1983-10-20 1983-10-20 印刷配線板

Publications (2)

Publication Number Publication Date
JPS6088492A JPS6088492A (ja) 1985-05-18
JPH0345909B2 true JPH0345909B2 (cg-RX-API-DMAC7.html) 1991-07-12

Family

ID=16356545

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58196360A Granted JPS6088492A (ja) 1983-10-20 1983-10-20 印刷配線板

Country Status (1)

Country Link
JP (1) JPS6088492A (cg-RX-API-DMAC7.html)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0828559B2 (ja) * 1987-04-23 1996-03-21 松下電器産業株式会社 印刷配線板
JPH0793481B2 (ja) * 1988-03-23 1995-10-09 松下電器産業株式会社 金属ベース印刷配線板
JPH0391989A (ja) * 1989-09-04 1991-04-17 Matsushita Electric Ind Co Ltd 金属基板

Also Published As

Publication number Publication date
JPS6088492A (ja) 1985-05-18

Similar Documents

Publication Publication Date Title
US6625037B2 (en) Printed circuit board and method manufacturing the same
JP3360772B2 (ja) 微細電極の接続構造および微細電極を持つ電子部品の検査方法
CN111919520A (zh) 电子电路装置以及电路基板的制造方法
JPH0345909B2 (cg-RX-API-DMAC7.html)
JP3178417B2 (ja) 半導体キャリアおよびその製造方法
JP3743716B2 (ja) フレキシブル配線基板及び半導体素子の実装方法
JP3833084B2 (ja) 電子部品実装用フィルムキャリアテープの製造方法
JPS6092690A (ja) ガラスエポキシベ−ス印刷配線板
JPH0433154B2 (cg-RX-API-DMAC7.html)
JP2607906B2 (ja) 回路基板
JPS60120588A (ja) 印刷配線板
JP2003023223A (ja) 回路用金属基板及び半導体装置
JPH1146056A (ja) 電子部品装置
JPS6113690A (ja) 相互接続回路板の製造法
JPH0738492B2 (ja) フレキシブル配線基板
JP2002335070A (ja) プリント配線板及びその製造方法並びにそれを用いた電子部品の接続方法
JP2986466B2 (ja) 回路基板平坦化方法及び半導体装置の製造方法
JPH10219213A (ja) 導電性接着剤および回路基板に電気部品を実装する方法
JPS62291086A (ja) 配線回路基板
JPS6346592B2 (cg-RX-API-DMAC7.html)
JP2001068815A (ja) 配線板とその製造方法
JP3024339B2 (ja) 電子部品の組立方法
JPH02304945A (ja) 半導体素子の実装方法
JPH03216972A (ja) 低抵抗エラスチックコネクター及びその製造方法
JPH0834343B2 (ja) 回路基板並びにその製造方法