JPS6088492A - Printed circuit board - Google Patents

Printed circuit board

Info

Publication number
JPS6088492A
JPS6088492A JP58196360A JP19636083A JPS6088492A JP S6088492 A JPS6088492 A JP S6088492A JP 58196360 A JP58196360 A JP 58196360A JP 19636083 A JP19636083 A JP 19636083A JP S6088492 A JPS6088492 A JP S6088492A
Authority
JP
Japan
Prior art keywords
resin layer
resin
printed
paste
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58196360A
Other languages
Japanese (ja)
Other versions
JPH0345909B2 (en
Inventor
瑛一 綱島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58196360A priority Critical patent/JPS6088492A/en
Publication of JPS6088492A publication Critical patent/JPS6088492A/en
Publication of JPH0345909B2 publication Critical patent/JPH0345909B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体素子、抵抗素子、容量素子。[Detailed description of the invention] Industrial applications The present invention relates to a semiconductor element, a resistive element, and a capacitive element.

インダクタンス素子などのチップ部品をワイヤボンディ
ング技術によって接続するのに適した印刷配線板の構造
に関する。
The present invention relates to the structure of a printed wiring board suitable for connecting chip components such as inductance elements by wire bonding technology.

従車ωルハ*1.#罰t−シの[則り白よ従来、印刷配
線板にチップ部品を装着した状態をチップオンボード技
術といって一部の従来例があった。すなわち、第1の例
として、第1図に示すように、アルミニウム板1に空孔
3を伴なったアルマイト化絶縁層2を形成したのち、銅
箔用接着剤層4を介して全面に銅箔5を接着形成し、つ
いで、選択的に銅箔をエツチングした導体部分5に対し
てニッケル6、又は金7めっきを行ないアルミ線をワイ
ヤボンディングしたものがある。
Follower vehicle ω Luha *1. #Punishment T-C [Punishment] In the past, there were some conventional examples of chip-on-board technology, which refers to the state in which chip components are mounted on a printed wiring board. That is, as a first example, as shown in FIG. There is a method in which a foil 5 is bonded and then the conductor portion 5 is selectively etched with copper foil, and the conductor portion 5 is plated with nickel 6 or gold 7, and an aluminum wire is wire-bonded.

また、第2の例として第2図に示すようにガラス布基材
エポキシ樹脂積層板12に、銅箔をダイレクトに被着し
たのち、選択的に銅箔をエツチングした部分13に対し
て金めつき部1・4を形成し、ワイヤボンディングしだ
ものがある。
As a second example, as shown in FIG. 2, copper foil is directly adhered to the glass cloth base epoxy resin laminate 12, and then gold plating is applied to the selectively etched portions 13 of the copper foil. There are bonded parts 1 and 4 and wire bonding parts.

これらの従来例の問題点として第1の例ではアルマイト
処理有孔部に水分が吸着又はトラップされて基板の絶縁
性を低め電気的短絡をひきおこすこと、金線とアルミ線
との併用ボンディングが困難又は面倒であること、銅箔
の選択的エツチングやニッケルめっき時の浴の工程が複
雑でコスト高となること、°浴中のイオン性物質の残溜
から半導体チップの汚染を招き寿命を短かくする可能性
大なることなどが挙げられる。捷だ、第2の例では銅箔
をダイレクトに被着したため積層板中のガラスせんい布
の網目が銅箔面にレプリカされて凹凸を生じワイヤボン
ディング機構の円滑な運転に支障を来たすこと、金めつ
き浴の汚染のあること、金が高価であることなどの問題
点が挙げられる。
The problems with these conventional methods are that in the first example, moisture is adsorbed or trapped in the alumite treated perforated parts, lowering the insulation of the board and causing electrical short circuits, and it is difficult to bond together gold wire and aluminum wire. Otherwise, selective etching of copper foil and bath processes during nickel plating are complicated and costly, and residual ionic substances in the bath can contaminate semiconductor chips and shorten their lifespan. There are many things that are likely to happen. Unfortunately, in the second example, because the copper foil was applied directly, the mesh of the glass fiber cloth in the laminate was replicated on the copper foil surface, creating unevenness and hindering the smooth operation of the wire bonding mechanism. Problems include the contamination of the plating bath and the high cost of gold.

発明の目的 本発明は、金属板に対するものであって前述の従来例の
欠点を解消し、簡素で、かつ、経済的なワイヤボンディ
ング用の印刷配線板を得る事を目的とする。
OBJECTS OF THE INVENTION The present invention is directed to metal plates, and aims to eliminate the drawbacks of the conventional examples described above and to obtain a simple and economical printed wiring board for wire bonding.

発明の構成 本発明の構成としては、第1に金属と親和性の良い可撓
性の絶縁性樹脂ペーストを金属板にダイレクトに印刷し
て第11!f脂層を形成し、第2に前記第1樹脂層面上
に、選択的に、高絶縁性のリジッドな樹脂ペーストを印
刷し第2樹脂層とし、第3に前記第2樹脂層の選択的印
刷面をはみ出さ々い範囲で導電性粒子を含む樹脂ペース
トを選択的に印刷した第3樹脂層をそなえたものである
。各樹脂層の形成に印刷技術を使用するのは、必要な印
刷厚さ10〜150ミクロンを±2〜6ミクロンの高精
度に維持するためである。また第2および第3の樹脂層
の印刷は、厚さ方向だけでなく水平方向に対して0.0
1〜0.1w以内の幅許容差におさめるために、メツシ
ュスクリーン製版の技術が有効である。なお、本発明の
構成には、第1゜第2.第3の各樹脂層の印刷後、60
〜80°Cの予熱後、120〜220″Cの温度で気中
加熱し硬化する工程が付随する。
Structure of the Invention As a structure of the present invention, firstly, a flexible insulating resin paste having good affinity with metal is directly printed on a metal plate. f. forming a resin layer; secondly, selectively printing a highly insulating rigid resin paste on the surface of the first resin layer to form a second resin layer; and thirdly, selectively printing the second resin layer. A third resin layer is provided in which a resin paste containing conductive particles is selectively printed in an area that extends beyond the printed surface. The reason why printing technology is used to form each resin layer is to maintain the required printing thickness of 10 to 150 microns with high precision of ±2 to 6 microns. In addition, the printing of the second and third resin layers is 0.00% not only in the thickness direction but also in the horizontal direction.
In order to keep the width tolerance within 1 to 0.1 w, mesh screen plate making technology is effective. Note that the configuration of the present invention includes a first degree, a second degree, and a second degree. After printing each third resin layer, 60
After preheating to ~80°C, there is an accompanying step of curing by heating in air at a temperature of 120-220″C.

実施例の説明 第3図、第4図は本発明実施例の各断面図である0 まず、厚さ1 @ Omm、大きさ60X60謳のアル
ミニウム板2汚れ・ごみ等をアセトン液にて拭きとる。
DESCRIPTION OF THE EMBODIMENT FIGS. 3 and 4 are cross-sectional views of the embodiments of the present invention. First, an aluminum plate 2 with a thickness of 1 Omm and a size of 60 x 60 is wiped off with an acetone solution to remove dirt, dust, etc. .

そして、このアルミニウム板22に、第1411脂層2
3として、エポキシ樹脂(例えば、シェル石油社の製品
名、828 )に対し、芳香族アミンアダクト樹脂(日
本合成化工社製H−84)を60phr添加した粘度3
50ボイズの無溶剤型樹脂ペーストラテトロンメツシュ
スクリーンの180メ、ンシュを使用して、厚さ20±
2μとして全面に印刷し、130″Cにて30分大気中
で硬化する。この第1樹脂層23の厚さは14±1μで
、その硬度は、鉛筆硬度4H以上で全橋板中央のそり偏
位10咽に耐える可撓性を有しており、接着強度:も1
20°Cで6kg/−と高い。
Then, on this aluminum plate 22, the 1411th fat layer 2
As 3, viscosity 3 is obtained by adding 60 phr of aromatic amine adduct resin (H-84 manufactured by Nippon Gosei Kako Co., Ltd.) to an epoxy resin (for example, 828, a product name of Shell Oil Co., Ltd.).
Using a 50-void solvent-free resin paste lattetron mesh screen with a thickness of 20±
The first resin layer 23 has a thickness of 14±1μ, and its hardness is 4H or more on a pencil hardness, which prevents warpage in the center of the entire bridge board. It has the flexibility to withstand 10 degrees of deviation, and has an adhesive strength of 1.
It is as high as 6 kg/- at 20°C.

第2樹脂層24として、エポキシ樹脂(シェル石油社8
28)に対し芳香族アミンダクト樹脂(日本合成加工社
製H−90)を60phr添加した粘度1100ポイズ
の無溶剤型樹脂ペーストを使用して、テトロンの160
メソシユスクリーンに選択レジスト膜を厚さ6o±2μ
に形成したものを使用して厚さ35±2μに選択的に、
前記第1樹脂層23の上に重ねて印刷し150″GKで
180分大気中で硬化する。この第2樹脂層24の厚さ
は24±2μで、硬度は、鉛筆硬度6H以上で、ガラス
転移温度TGは180°Cを有しているが金属板中央の
そり偏位10mmに耐える可撓性は有していない。
As the second resin layer 24, an epoxy resin (Shell Oil Company 8
Using a solvent-free resin paste with a viscosity of 1100 poise to which 60 phr of aromatic amine duct resin (H-90 manufactured by Nippon Gosei Kogyo Co., Ltd.) was added to 28), Tetron's 160
Selective resist film on mesh screen to thickness 6o±2μ
selectively to a thickness of 35±2μ using
The second resin layer 24 is printed on top of the first resin layer 23 and cured in the atmosphere for 180 minutes at 150'' GK.The thickness of the second resin layer 24 is 24±2μ, the hardness is 6H or more on the pencil hardness, and it is hardened with glass. Although the transition temperature TG is 180°C, the metal plate does not have the flexibility to withstand a warping deviation of 10 mm at the center.

第3樹脂層26として、フレーク状銀粉の平均大きさ1
〜6μを重量比にして86パーセントをエポキシ樹脂(
シェル石油社製10o1)に、硬化剤として、変性酸無
水物(日本合成化工社製H−106)を80phr添加
した樹脂ペーストにミキサーを用いて混合して粘度16
0ポイズの導電性イi4脂ペーストを使用して、テトロ
ンの180メツシユスクリーンに選択レジスト膜を厚さ
25±2μに形成したものを使用して厚さ19±2μに
選択印刷し150″Cにて60分大気中で硬化する。
As the third resin layer 26, the average size of flaky silver powder is 1
86% epoxy resin (with a weight ratio of ~6μ)
10o1 (manufactured by Shell Oil Company) and 80 phr of modified acid anhydride (H-106, manufactured by Nippon Gosei Kako Co., Ltd.) as a curing agent was added to the resin paste using a mixer to obtain a viscosity of 16.
Using 0 poise conductive I4 fat paste, selectively print to a thickness of 19±2μ using a Tetron 180 mesh screen with a selective resist film formed to a thickness of 25±2μ and 150″C. Cure in air for 60 minutes.

この第3樹脂層26の厚さは14±2μで硬度は、鉛筆
硬度8H以上で、ガラス転移温度(Ta )は210″
Cで導体抵抗値は10mΩ/口である。第2、第3樹脂
層の硬度増加は超音波エネルギーの散逸防止に効果的と
みられる。
The third resin layer 26 has a thickness of 14±2μ, a pencil hardness of 8H or more, and a glass transition temperature (Ta) of 210″.
C and the conductor resistance value is 10 mΩ/mouth. Increased hardness of the second and third resin layers appears to be effective in preventing dissipation of ultrasonic energy.

半導体IC用のワイヤボンディング装置の市販品を用い
て金線用の超音波併用熱圧着ボンデイング装置により、
金細線26およびアルミ細線28を、ボンティングし、
その強度試験をおこなった結果を次表に示す、実用基準
6g以上が得られる。
Using a commercially available wire bonding device for semiconductor ICs, an ultrasonic thermocompression bonding device for gold wire is used.
Bonding the thin gold wire 26 and the thin aluminum wire 28,
The results of the strength test are shown in the table below, and a practical standard of 6 g or more was obtained.

なお、導電性樹脂層26の表面をスクラツプして平担化
すればボンディング性は更に改善される。
Note that the bonding properties can be further improved by scraping the surface of the conductive resin layer 26 to make it flat.

また同時に銀2パーセント入りの錫−鉛(61/37)
はんだ30での半導体チップ31の接着は、220〜2
80’C数秒の処理で可能となる。
At the same time, tin-lead containing 2% silver (61/37)
The adhesion of the semiconductor chip 31 with the solder 30 is 220~2
80'C can be done in a few seconds.

発明の効果 本発明により、金属板の表面処理にアルマイト処理の如
き特殊加工を施こさずに充分な接着強度が得られるので
、処理中への水分の吸着やトラップの可能性をなくシタ
こと、金線とアルミ線との併用ボンディングが可能であ
ること、導体の形成力)” ラ4 工aででき、工程が
簡素化され経済的であると同時にエツチング液やめっき
液の残溜からくる搭載した半導体チップの汚染と寿命特
性低下の問題が避けられる0まだ導電樹脂層の面は平担
で、鏡面研磨加工も可能となるO高価な金めつき浴を避
け、導電性樹脂に内臓する銀に対して金に替えてボンデ
ィングを行なう事ができる。このように本発明による印
刷配線板は、金属ベースを絶縁化し、導体をエツチング
でなく直接印刷しドライエ法で形成でき、表面実装素子
のワイヤボンディングを可能ならしめた技術的にも経済
的にもすぐれたものである0
Effects of the Invention According to the present invention, sufficient adhesive strength can be obtained without applying special processing such as alumite treatment to the surface of the metal plate, eliminating the possibility of moisture adsorption or trapping during treatment. It is possible to bond gold wires and aluminum wires together, and the ability to form conductors). The problem of contamination of semiconductor chips and deterioration of life characteristics can be avoided.The surface of the conductive resin layer is still flat, and mirror polishing is also possible. As described above, the printed wiring board according to the present invention can be formed by insulating the metal base and directly printing the conductor instead of etching, using the dryer method, and can be used to bond the wires of surface mount devices. It is a technologically and economically superior technology that has made bonding possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図はそれぞれ従来例の断面図、第3図
および第4図は本発明の各実施例断面図である。 22・・・・・・アルミニウム板、23・・・・・・絶
縁性樹脂第1層、24・・・・・・絶縁性樹脂第2層、
26・・・・・・導電性第3層。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第3図 ′、゛、・ 第4図 乙〜22
FIGS. 1 and 2 are sectional views of a conventional example, and FIGS. 3 and 4 are sectional views of each embodiment of the present invention. 22... Aluminum plate, 23... Insulating resin first layer, 24... Insulating resin second layer,
26... Conductive third layer. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3', ゛,・ Figure 4 O-22

Claims (1)

【特許請求の範囲】[Claims] 金属板に絶縁性樹脂ペーストを印刷した第1樹脂層と、
この第1樹脂層上に絶縁性樹脂ペーストを選択的に重な
るように印刷した第2樹脂層および前記第2樹脂層上に
これと同一かもしくはこれからはみ出さない範囲に導電
性樹脂ペーストを印刷した第3樹脂層をそなえ、前記第
3樹脂層に対して、半導体チップの電極接続用の金線又
はアルミ線を熱圧着ボンディングした事を特徴とする印
刷配線板。
a first resin layer in which an insulating resin paste is printed on a metal plate;
A second resin layer was printed with an insulating resin paste selectively overlapping the first resin layer, and a conductive resin paste was printed on the second resin layer either in the same area or in an area that did not protrude from the second resin layer. 1. A printed wiring board comprising a third resin layer, and a gold wire or aluminum wire for connecting an electrode of a semiconductor chip is thermocompression bonded to the third resin layer.
JP58196360A 1983-10-20 1983-10-20 Printed circuit board Granted JPS6088492A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58196360A JPS6088492A (en) 1983-10-20 1983-10-20 Printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58196360A JPS6088492A (en) 1983-10-20 1983-10-20 Printed circuit board

Publications (2)

Publication Number Publication Date
JPS6088492A true JPS6088492A (en) 1985-05-18
JPH0345909B2 JPH0345909B2 (en) 1991-07-12

Family

ID=16356545

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58196360A Granted JPS6088492A (en) 1983-10-20 1983-10-20 Printed circuit board

Country Status (1)

Country Link
JP (1) JPS6088492A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63265486A (en) * 1987-04-23 1988-11-01 Matsushita Electric Ind Co Ltd Printed circuit board
JPH01241195A (en) * 1988-03-23 1989-09-26 Matsushita Electric Ind Co Ltd Metal based printed wiring board
JPH0391989A (en) * 1989-09-04 1991-04-17 Matsushita Electric Ind Co Ltd Metal board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63265486A (en) * 1987-04-23 1988-11-01 Matsushita Electric Ind Co Ltd Printed circuit board
JPH01241195A (en) * 1988-03-23 1989-09-26 Matsushita Electric Ind Co Ltd Metal based printed wiring board
JPH0391989A (en) * 1989-09-04 1991-04-17 Matsushita Electric Ind Co Ltd Metal board

Also Published As

Publication number Publication date
JPH0345909B2 (en) 1991-07-12

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