JPS6092691A - Film base printed circuit board - Google Patents

Film base printed circuit board

Info

Publication number
JPS6092691A
JPS6092691A JP58201618A JP20161883A JPS6092691A JP S6092691 A JPS6092691 A JP S6092691A JP 58201618 A JP58201618 A JP 58201618A JP 20161883 A JP20161883 A JP 20161883A JP S6092691 A JPS6092691 A JP S6092691A
Authority
JP
Japan
Prior art keywords
resin
resin layer
printing
circuit board
printed circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58201618A
Other languages
Japanese (ja)
Other versions
JPH0433154B2 (en
Inventor
瑛一 綱島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58201618A priority Critical patent/JPS6092691A/en
Publication of JPS6092691A publication Critical patent/JPS6092691A/en
Publication of JPH0433154B2 publication Critical patent/JPH0433154B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125Reinforcing structures
    • H01L2224/10126Bump collar
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体素子、抵抗素子、容量素子。[Detailed description of the invention] Industrial applications The present invention relates to a semiconductor element, a resistive element, and a capacitive element.

インダクタンス素子などのチップ部品をワイアボンディ
ング技術によって接続するのに適した印刷配線板の構造
に関する。
The present invention relates to the structure of a printed wiring board suitable for connecting chip components such as inductance elements by wire bonding technology.

従来例の構成とその問題点 従来、印刷配線板にチップ部品を装着した状態をチップ
オンボード技術といって一部の従来例があった。すなわ
ち第1の例として第1図に示すようにポリイミドフィル
ム板1に粗面3を作シ出す放電加工処理層2を形成した
のち、銅箔用接着剤層4を介して全面に銅箔6を接着形
成し、さらに、選択的にとの銅箔をエツチングした導体
部分5に対してニッケル6、又は金7めっきを行ない、
アルミニウム細線をワイアボンディングしたものがある
。また第2の例として第2図に示すようにガラス布基材
エポキシ樹脂積層板12に、銅箔をダイレクトに被着し
たのち、選択的にこの銅箔をエツチングした部分に対し
て金めつきを行ない波状面の凹凸面14を有する導体1
3を得て、これに金線を12イアボンデイングしたもの
がある。これらの従来例の問題点として第1の例では、
アルマイト処理有孔部に水分が吸着又はトラップされて
基板の絶縁性を低め電気的短絡をひきおこすこと、金線
とアルミ線との併用ボンディングが困難又は面倒である
こと、銅箔の選択的エツチングやニツケルめっき時の浴
の工程が複雑でコスト高となること、浴中のイオン性物
質の残溜から半導体チップの汚染番招き寿命を短かくす
る可能性大なることなどが挙げられる。また第2の例で
は、銅箔をダイレクトに被着したため積層板中のガラス
せんい布の網目が銅箔面にレプリカされて凹凸を生じワ
イアボンディング機構の円滑な運転に支障を来たすこと
、金めつき浴の汚染のあること、金が高価であることな
どの問題点が挙げられる。
Structures of conventional examples and their problems In the past, there have been some conventional examples of a state in which chip components are mounted on a printed wiring board, which is called chip-on-board technology. That is, as a first example, as shown in FIG. 1, after forming an electrical discharge processing layer 2 that creates a rough surface 3 on a polyimide film plate 1, a copper foil 6 is applied to the entire surface via a copper foil adhesive layer 4. The conductor portion 5 on which the copper foil is selectively etched is then plated with nickel 6 or gold 7,
There are wire-bonded aluminum wires. As a second example, as shown in FIG. 2, copper foil is directly adhered to the glass cloth base epoxy resin laminate 12, and then gold plating is applied to selectively etched portions of the copper foil. Conductor 1 having an uneven surface 14 having a wavy surface
3 was obtained, and 12-ear bonding of gold wire was made to this. The problem with these conventional examples is that in the first example,
Moisture is adsorbed or trapped in the alumite treated perforated parts, lowering the insulation properties of the board and causing electrical short circuits, bonding with gold wire and aluminum wire is difficult or troublesome, selective etching of copper foil, etc. The bath process during nickel plating is complicated and costly, and the residual ionic substances in the bath may contaminate the semiconductor chip and shorten its lifespan. In addition, in the second example, since the copper foil was directly adhered, the mesh of the glass fiber cloth in the laminate was replicated on the copper foil surface, causing unevenness and impeding the smooth operation of the wire bonding mechanism. Problems include the fact that the bathtub is contaminated and gold is expensive.

発明の目的 本発明の対象は有機樹脂フィルム板に対するものであっ
て前述の従来例の欠点を解消し簡素でかつ経済的なワイ
アボンディング用の可撓性の配線板を得る事を目的とす
る。
OBJECTS OF THE INVENTION The object of the present invention is to solve the drawbacks of the above-mentioned conventional examples and to obtain a simple and economical flexible wiring board for wire bonding.

発明の構成 本発明の構成としては、第1にポリエステル・ポリイミ
ドなどのフィルムと親和性の良い可撓性の絶縁性樹脂ペ
ーストを有機樹脂フィルムにダイレクトに印刷して第1
樹脂層を形成し、第2に前記第1樹脂層面上に選択的に
、高絶縁性のリジッドな樹脂ペーストを印刷し第2樹脂
層とし、第3に前記第2樹脂層の選択的印刷面をはみ出
さない範囲で導電性粒子を含む樹脂ペーストを選択的に
印i”s3樹脂層を各樹脂層の形成に印刷技術を使用す
るのは、必要な印刷厚さ10〜150ミクロンを±2〜
6ミクロンの高精度に維持するためである。また第2お
よび第3の樹脂層の印刷には、厚さ方向だけでなく水平
方向に対して0.01〜0.1 mm以内の幅許容差に
おさめるためにメッシエスクリーン製版の技術が有効で
ある。なお、本発明の構成には、第1.第2.第3の各
樹脂層の印刷後60〜80℃の予熱後、120〜220
°Cの温度で気中加熱し硬化する工程が伺随する。
Structure of the Invention As a structure of the present invention, firstly, a flexible insulating resin paste having good affinity with films such as polyester and polyimide is directly printed on an organic resin film.
forming a resin layer, secondly printing a highly insulating rigid resin paste selectively on the surface of the first resin layer to form a second resin layer, and thirdly selectively printing a surface of the second resin layer. The resin paste containing conductive particles is selectively printed within a range that does not protrude. Printing technology is used to form each resin layer, so that the required printing thickness is 10 to 150 microns ± 2. ~
This is to maintain a high precision of 6 microns. In addition, for printing the second and third resin layers, Messier screen plate making technology is effective in order to keep the width tolerance within 0.01 to 0.1 mm not only in the thickness direction but also in the horizontal direction. It is. Note that the configuration of the present invention includes the first. Second. After printing each third resin layer and preheating at 60-80℃, 120-220℃
A process of curing by heating in the air at a temperature of °C is involved.

実施例の説明 第3図、第4図は本発明の実施例各所面図である。まず
、厚さ60ミクロン、大きさ50X50間のポリイミド
板22の汚れ・ごみ等をアセトン液にて拭きとる。
DESCRIPTION OF EMBODIMENTS FIGS. 3 and 4 are plan views of various parts of an embodiment of the present invention. First, dirt, dust, etc., on the polyimide plate 22 with a thickness of 60 microns and a size of 50×50 are wiped off with an acetone solution.

そして、このアルミニウム板22に、第1樹脂層として
、エポキシ樹脂(例えば、シェル石油社の製品名828
)に対し芳香族アミンアダクト樹脂(日本合成化工社製
、H−84)を70phr添加した粘度360ポイズの
無溶剤型樹脂ペーストをテトロンメツシュスクリーンの
180メツシユを使用して、厚さ20±2μとして全面
に印刷し、130℃にて30分大気中で硬化する。この
第1樹脂層23の厚さは14±1μで、硬度は鉛筆硬度
4H以上でフィルムの直径O,SWmの丸棒をはさんだ
折シ曲げに耐える可撓性を有しており接着強度も120
℃で2 Kp / mtAと高い。
This aluminum plate 22 is coated with an epoxy resin (for example, Shell Oil Company's product name 828) as a first resin layer.
) to which 70 phr of aromatic amine adduct resin (manufactured by Nippon Gosei Kako Co., Ltd., H-84) was added and the viscosity was 360 poise. The sample was printed on the entire surface and cured in the air at 130°C for 30 minutes. This first resin layer 23 has a thickness of 14±1 μm, a pencil hardness of 4H or more, and has the flexibility to withstand bending when a round bar with a diameter of O, SWm is sandwiched between the films, and has adhesive strength as well. 120
As high as 2 Kp/mtA at ℃.

第2樹脂層24として、エポキシ樹脂(シェル石油社8
28)に対し芳香族アミンアダクト樹脂(i本合成加上
杆gH−so)を60phr 添加した粘度1100ポ
イズの無溶剤型樹脂ペーストを使用して、テトロンの1
60メツシユスクリーンに選択レジスト膜を厚さ6o±
2μに形成したものを使用して厚さ36±2μに選択的
に、前記第1樹脂層の上に重ねて印刷し150℃にて1
80分大気中で硬化する。この第2樹脂層24の厚さは
24±2μで、その硬度は、鉛筆硬度6H以上で、ガラ
ス転移温度TGは180℃を有しているがフィルム板中
央のそノ偏位101rrIn程度に耐える可撓性を有し
ている。
As the second resin layer 24, an epoxy resin (Shell Oil Company 8
Using a solvent-free resin paste with a viscosity of 1100 poise to which 60 phr of aromatic amine adduct resin (ihonsei Kajo gH-so) was added to 28), 1 of Tetron was added.
Selective resist film on 60mesh screen with thickness 6o±
The first resin layer was selectively printed to a thickness of 36±2μ using a layer formed to have a thickness of 2μ, and then printed at 150°C.
Cure in air for 80 minutes. The second resin layer 24 has a thickness of 24±2μ, a pencil hardness of 6H or more, and a glass transition temperature TG of 180°C, but can withstand a deviation of about 101rrIn at the center of the film plate. It has flexibility.

第3樹脂層25としてフレーク状銀粉の平均大きさ1〜
5μを重量比にして86パーセントをエポキシ樹脂(シ
ェル石油社製1001)に、硬化剤として変性酸無水物
(日本合成化工社製H−106)を80phr添加した
樹脂ペーストにミキサーを用いて混合して粘度150ポ
イズの導電性樹脂ペーストを使用して、テトロンの18
0メツシユスクリーンに選択レジスト膜を厚さ26±2
μに形成したものを使用して厚さ19±2μに選択印刷
し150℃にて60分大気中で硬化する。
The average size of the flaky silver powder as the third resin layer 25 is 1 to
Using a mixer, mix a resin paste containing 86% epoxy resin (1001 manufactured by Shell Oil Co., Ltd.) and 80 phr of modified acid anhydride (H-106 manufactured by Nippon Gosei Kako Co., Ltd.) as a hardening agent, based on a weight ratio of 5μ. Using a conductive resin paste with a viscosity of 150 poise,
0 mesh screen with selected resist film thickness 26±2
Using the material formed in μ, selective printing was performed to a thickness of 19±2 μ and cured at 150° C. for 60 minutes in the air.

この第3樹脂層26の厚さは14±2μで、硬度は、鉛
筆硬度8H以上で、ガラス転移温度TGは210℃で導
体抵抗値は10mΩ/口である。
The third resin layer 26 has a thickness of 14±2 μm, a pencil hardness of 8H or more, a glass transition temperature TG of 210° C., and a conductor resistance value of 10 mΩ/mouth.

第2.第3樹脂層の硬度増加は超音波エネルギーの散逸
防止に効果的とみられる半導体IC用のワイアボンディ
ング装置の市販品を用いて金線用の超音波併用熱圧着ボ
ンディング装置によシ金細線26およびアルミニウム細
線28をボンディングし、その強度試験をおこなった結
果を次表に示す。
Second. The increase in the hardness of the third resin layer is achieved by using a commercially available wire bonding device for semiconductor ICs, which is considered to be effective in preventing the dissipation of ultrasonic energy.The thin gold wire 26 and The aluminum thin wire 28 was bonded and a strength test was conducted, and the results are shown in the following table.

実用基準6g以上が得られる。A practical standard of 6g or more can be obtained.

なお、導電性樹脂層26の表面をスクラップして平坦化
すればボンディング性は更に改善される。
Note that if the surface of the conductive resin layer 26 is scraped and flattened, the bonding properties will be further improved.

また同時に銀2パーセント入りの錫−鉛(61/37)
はんだ30での半導体チップ31の接着は、220〜2
80℃数秒の処理で可能となる。
At the same time, tin-lead containing 2% silver (61/37)
The adhesion of the semiconductor chip 31 with the solder 30 is 220~2
This can be done by processing at 80°C for a few seconds.

発明の効果 本発明により、ポリイミドフィルム表面処理に放電加工
処理の如き特殊加工を施こさずに充分な接着強度が得ら
れるので、ポリイミドフィルム特有の水分の吸着やトラ
ップの可能性をなくしたこと、金線とアルミ線との併用
ボンディングが可能であること、導体の形成がドライ工
程ででき、工栽メ品4:(ヒゴA(経済的であると同時
にエツチング液やめっき液の残溜からくる搭載した半導
体チップの汚染と寿命特性低下の問題が避けられる。ま
た導電性樹脂層の面は平坦で、鏡面研磨加工も可能とな
る。高価な金めつき浴を避け、導電性樹脂に内蔵する銀
に対して金に替えてボンディングを行なう事ができる。
Effects of the Invention According to the present invention, sufficient adhesive strength can be obtained without performing special processing such as electric discharge machining on the surface of the polyimide film, thereby eliminating the possibility of water adsorption and trapping that is characteristic of polyimide films. It is possible to bond gold wire and aluminum wire together, the conductor can be formed in a dry process, and the manufactured product 4: (Higo A) is economical and at the same time is free from residual etching solution and plating solution. This avoids the problems of contamination of the mounted semiconductor chip and deterioration of its life characteristics.Also, the surface of the conductive resin layer is flat and mirror polishing is possible.It avoids expensive gold plating baths and is built into the conductive resin. It is possible to bond silver to gold.

このように本発明による印刷配線板はフィルムベースを
高耐湿化し、導体をエツチングでなく直接印刷しドライ
エ法で形成でき、表面実装素子のワイアボンディングを
可能ならしめた技術的にも経済的にもすぐれたものであ
る。
As described above, the printed wiring board according to the present invention has a film base with high moisture resistance, conductors can be directly printed instead of etched, and can be formed using the dryer method, making wire bonding of surface mount devices possible, which is technically and economically advantageous. It is excellent.

【図面の簡単な説明】[Brief explanation of drawings]

第1図および第2図はそれぞれ従来例の断面図、第3図
および第4図は本発明の各実施例断面図である。 22・・・・・・アルミニウム板、23・・・・・・絶
縁性樹脂第1層、24・・・・・・絶縁性樹脂第2層、
26・・・・・・導電性第3層。
FIGS. 1 and 2 are sectional views of a conventional example, and FIGS. 3 and 4 are sectional views of each embodiment of the present invention. 22... Aluminum plate, 23... Insulating resin first layer, 24... Insulating resin second layer,
26... Conductive third layer.

Claims (1)

【特許請求の範囲】[Claims] 有機フィルム板に対して絶縁性樹脂ペーストを印刷形成
した可撓性の第1樹脂層、絶縁性樹脂ペーストを選択的
に重ねて印刷形成した非可撓性の第2樹脂層および前記
第2樹脂層と同じ面積からはみ出さない範囲に導電性樹
脂を印刷形成した第3樹脂層をそなえ、前記3層の樹脂
層構成部分の最上層に対して、半導体チップの電極接続
用の金線又はアルミ線を熱圧着ボンディングした事を特
徴とするフィルムベース印刷配線板。
A flexible first resin layer formed by printing an insulating resin paste on an organic film plate, a non-flexible second resin layer formed by printing and selectively overlapping an insulating resin paste, and the second resin. A third resin layer is provided by printing a conductive resin in an area that does not protrude from the same area as the third resin layer, and a gold wire or aluminum wire for connecting the electrodes of the semiconductor chip is provided to the top layer of the three resin layer constituent parts. A film-based printed wiring board characterized by thermocompression bonding of wires.
JP58201618A 1983-10-27 1983-10-27 Film base printed circuit board Granted JPS6092691A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58201618A JPS6092691A (en) 1983-10-27 1983-10-27 Film base printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58201618A JPS6092691A (en) 1983-10-27 1983-10-27 Film base printed circuit board

Publications (2)

Publication Number Publication Date
JPS6092691A true JPS6092691A (en) 1985-05-24
JPH0433154B2 JPH0433154B2 (en) 1992-06-02

Family

ID=16444040

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58201618A Granted JPS6092691A (en) 1983-10-27 1983-10-27 Film base printed circuit board

Country Status (1)

Country Link
JP (1) JPS6092691A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49108564A (en) * 1973-02-20 1974-10-16
JPS51123241A (en) * 1975-04-18 1976-10-27 Matsushita Electric Ind Co Ltd Method of coating conductive material on insulators
JPS5348462A (en) * 1976-10-15 1978-05-01 Hitachi Ltd Wire bonding method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49108564A (en) * 1973-02-20 1974-10-16
JPS51123241A (en) * 1975-04-18 1976-10-27 Matsushita Electric Ind Co Ltd Method of coating conductive material on insulators
JPS5348462A (en) * 1976-10-15 1978-05-01 Hitachi Ltd Wire bonding method

Also Published As

Publication number Publication date
JPH0433154B2 (en) 1992-06-02

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