JPS6077421A - 位置合わせ方法 - Google Patents

位置合わせ方法

Info

Publication number
JPS6077421A
JPS6077421A JP58186150A JP18615083A JPS6077421A JP S6077421 A JPS6077421 A JP S6077421A JP 58186150 A JP58186150 A JP 58186150A JP 18615083 A JP18615083 A JP 18615083A JP S6077421 A JPS6077421 A JP S6077421A
Authority
JP
Japan
Prior art keywords
alignment
pattern
mask
pattern image
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58186150A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0144009B2 (cs
Inventor
Hitoshi Hoshino
仁 星野
Tsuneo Funatsu
船津　恒雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58186150A priority Critical patent/JPS6077421A/ja
Publication of JPS6077421A publication Critical patent/JPS6077421A/ja
Publication of JPH0144009B2 publication Critical patent/JPH0144009B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
JP58186150A 1983-10-05 1983-10-05 位置合わせ方法 Granted JPS6077421A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58186150A JPS6077421A (ja) 1983-10-05 1983-10-05 位置合わせ方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58186150A JPS6077421A (ja) 1983-10-05 1983-10-05 位置合わせ方法

Publications (2)

Publication Number Publication Date
JPS6077421A true JPS6077421A (ja) 1985-05-02
JPH0144009B2 JPH0144009B2 (cs) 1989-09-25

Family

ID=16183252

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58186150A Granted JPS6077421A (ja) 1983-10-05 1983-10-05 位置合わせ方法

Country Status (1)

Country Link
JP (1) JPS6077421A (cs)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160122A (ja) * 1984-01-30 1985-08-21 Rohm Co Ltd サーマルプリントヘッドの製造方法
WO1997008588A1 (en) * 1995-08-23 1997-03-06 Micrel, Inc. Mask structure having offset patterns for alignment

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59208722A (ja) * 1983-05-13 1984-11-27 Oki Electric Ind Co Ltd 半導体集積回路装置用合せマ−ク

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59208722A (ja) * 1983-05-13 1984-11-27 Oki Electric Ind Co Ltd 半導体集積回路装置用合せマ−ク

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160122A (ja) * 1984-01-30 1985-08-21 Rohm Co Ltd サーマルプリントヘッドの製造方法
WO1997008588A1 (en) * 1995-08-23 1997-03-06 Micrel, Inc. Mask structure having offset patterns for alignment
US5747200A (en) * 1995-08-23 1998-05-05 Micrel, Incorporated Mask structure having offset patterns for alignment

Also Published As

Publication number Publication date
JPH0144009B2 (cs) 1989-09-25

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