JPS6073235U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6073235U
JPS6073235U JP16547283U JP16547283U JPS6073235U JP S6073235 U JPS6073235 U JP S6073235U JP 16547283 U JP16547283 U JP 16547283U JP 16547283 U JP16547283 U JP 16547283U JP S6073235 U JPS6073235 U JP S6073235U
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor equipment
pads
substantially circular
abstract
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16547283U
Other languages
English (en)
Inventor
萩本　英二
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP16547283U priority Critical patent/JPS6073235U/ja
Publication of JPS6073235U publication Critical patent/JPS6073235U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は本考案の第１実施例の上面図であって、キャビ
ティ部のみ示したものである。第２図は第１図に示す実
施例のＡ−Ａ’断面の要部拡大図である。第３図は本考
案の第２の実施例を示す上面図である。ここに、 １・・・・・・パッケージ、２・・・・・・半導体素子
搭載部、３・・・・・・半導体素子、４・・・・・・半
導体素子のパッド、５・・・・・・ボンディングワイヤ
ー、６・・・・・・パッケージの内部リード、７・・・
・・・外部リード、８・・・・・・金属板、９・・・・
・・放熱スタッド、１０・・・・・・封止面、１１・・
・・・・絶縁用セラミックス。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体素子上のパッドを略円形に配列し、かつ、半導体
    装置用パッケージの該半導体素子搭載部の体刑が前記半
    導体素子のパッドと同心円状に略円形となっていること
    を特徴とする半導体装置。
JP16547283U 1983-10-26 1983-10-26 半導体装置 Pending JPS6073235U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16547283U JPS6073235U (ja) 1983-10-26 1983-10-26 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16547283U JPS6073235U (ja) 1983-10-26 1983-10-26 半導体装置

Publications (1)

Publication Number Publication Date
JPS6073235U true JPS6073235U (ja) 1985-05-23

Family

ID=30362516

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16547283U Pending JPS6073235U (ja) 1983-10-26 1983-10-26 半導体装置

Country Status (1)

Country Link
JP (1) JPS6073235U (ja)

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