JPS6066459A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a power CMOS IC having a much more enhanced withstand voltage by a method wherein the drain diffusion layer of a transistor to be formed in a well is made as a diffusion layer deeper than diffusion depth of the drain of a transistor to be formed in a substrate. CONSTITUTION:An N type well 2 is formed in a P type semiconductor substrate 1, an N-channel transistor 3 having a source 5, a drain 6 and a gate 7, and a P- channel transistor 4 having a source 9, a drain 13 and a gate 11 are formed, and diffusion depth of the drain diffusion layer 13 is decided properly from the necessitating withstand voltage as deeper than the diffusion layer 6. Accordingly, the withstand voltage of the transistor 4 is enhanced, and a power CMOS IC having an enhanced withstand voltage can be obtained even when concentration of the well, etc. are not thinned.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a high breakdown voltage power MO8IC, and particularly to a power CMO8 IC with a well structure.

[Description of prior art]

Figure 1 shows a conventional power 0M using an offset structure.
A cross-sectional rfJ diagram of O8 engineering C is shown. For convenience of explanation, we will explain 0MO8 process 0 in which an N-type well was formed using a P-type semiconductor substrate;
The same applies to M08 Engineering C. 1 is a P-type semiconductor substrate on which 3 N-channel transistors are formed; 2 is a 4-P type semiconductor substrate;
This is an N-type well region where a channel transistor is formed.

5, 6, and 7 are the source, drain, and gate of the N-channel transistor, respectively, and 8 is the offset portion of the drain. Similarly, 9.10° and 11.12 are the source, drain, gate, and drain offsets of the P-channel transistor, respectively.

Now, the breakdown voltage of a transistor is the breakdown voltage of the drain diffusion layer (6 for N channel, 10 for P channel),
Drain offset section (N channel...8
．． Determined by the lower withstand voltage of P channel...12).

In the conventional power 0M08 with the structure shown in Fig. 1, the well concentration of 2 is one order of magnitude higher than the substrate concentration of 1, so the withstand voltage of the drain 10 formed in 2 is lower than that of 6. Therefore, there was a drawback that the breakdown voltage of the transistor 4 formed in the well 2 was lower than that of the transistor B formed in the substrate 1.

For example, in P type (100), the carrier density is 5×10''
' An N-channel transistor with an offset structure that uses a tTn-3 81 substrate and has a diffusion layer formed by thermal diffusion has a breakdown voltage of about 200V, whereas the surface concentration formed on this P-type substrate is Approximately 5X 10 "on-"
A P-channel transistor with an offset structure formed in the N-well has a breakdown voltage of only about 120V.

In this way, in the conventional power 0 MO8 process 0, CMO
Since the breakdown voltage of the BIO is determined by the breakdown voltage of the transistor formed in the well, there is a drawback that it is difficult to form a high breakdown voltage CMOBIO. In addition, in order to achieve a higher voltage resistance, it is necessary to reduce the Fertility, which has the disadvantages of increased puttiness and vulnerability to latch-up.

[Object of the present invention]

In order to solve these problems, the present invention improves the breakdown voltage by making the drain diffusion layer of the transistor formed in the well deeper than the diffusion depth of the drain of the transistor formed in the substrate. This provides an improved power output of 0M08.

Hereinafter, the present invention will be described in detail based on the drawings. [Embodiments of the present invention] FIG. 2 shows an embodiment of the present invention. 13 is a drain diffusion layer formed deeply according to the gist of the present invention.

Since there is a relationship between the depth of the diffusion layer and the breakdown voltage as shown in FIG. 6, the diffusion depth 13 is determined depending on the required breakdown pressure. 1 As described above, by forming the drain diffusion of the transistor formed in the well deeply, the breakdown voltage of the transistor formed in the well is improved, and the power supply with improved breakdown voltage can be achieved without disturbing the well concentration etc. MOBIO is obtained.

In Figure 2, only the drain 13 is deep, but since the source 9 and the drain 13 are usually formed at the same time, it goes without saying that the source 9 may also be formed deep.

In the above description, a transistor with an offset structure has been described, but it goes without saying that the present invention can also be applied to a transistor that does not have a set structure.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a conventional power CMOB transistor.
FIG. 2 is a sectional view of an embodiment of the present invention, and FIG. 6 is a relationship between diffusion depth and breakdown voltage. 1...P-type semiconductor substrate 2...N-well region 3...N-channel transistor 4...
P-channel transistor 5.9...Source 6.10...Drain 7.11...Gate 8.12...Drain offset portion 16...
...deep drain or more Applicant: Eiwa Seikosha Co., Ltd. Agent: Patent Attorney: Tsutomu Mogami Figure 1

Claims (1)

[Claims] (1) A well region of a second conductivity type is formed in a semiconductor substrate of a first conductivity type, and a transistor is formed in the semiconductor substrate and the well region. A semiconductor device characterized in that a drain diffusion N of a transistor formed in the semiconductor substrate is deeper than a drain diffusion layer of the transistor formed in the semiconductor substrate.