JPS63131562A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS63131562A JPS63131562A JP61278191A JP27819186A JPS63131562A JP S63131562 A JPS63131562 A JP S63131562A JP 61278191 A JP61278191 A JP 61278191A JP 27819186 A JP27819186 A JP 27819186A JP S63131562 A JPS63131562 A JP S63131562A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- integrated circuit
- circuit device
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 49
- 238000002955 isolation Methods 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 16
- 230000005669 field effect Effects 0.000 abstract description 13
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 108091006146 Channels Proteins 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 102000003691 T-Type Calcium Channels Human genes 0.000 description 1
- 108090000030 T-Type Calcium Channels Proteins 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置に係り、より詳しくはバイ
ポーラ素子と０ＭＯ８素子との複合素子（Ｂ１−０ＭＯ
８）からなる半導体集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and more specifically to a composite device of a bipolar element and a 0MO8 element (B1-0MO8 element).
8) A semiconductor integrated circuit device comprising:
バイポーラ素子と０ＭＯ８素子とが単一基板上に混在し
て形成される、いわゆるＢｉ−ＣＭＯ８半導体集積回路
装置においては、素子間の分離、例えばバイポーラ素子
領域とＰＭＯ８素子領域、あるいはバイポーラ素子領域
とバイポーラ素子領域の素子分離が重要である。In a so-called Bi-CMO8 semiconductor integrated circuit device in which bipolar elements and 0MO8 elements are mixedly formed on a single substrate, there is separation between the elements, for example, a bipolar element region and a PMO8 element region, or a bipolar element region and a bipolar element region. Element isolation in the element region is important.
以下、従来のＢ１−０ＭＯ８半導体集積回路装置の一実
施例につき、図面を参照して説明する。Hereinafter, one embodiment of a conventional B1-0MO8 semiconductor integrated circuit device will be described with reference to the drawings.
第２図は、Ｐ型基板上に形成されたｎ型エピタキシャル
層Ｖこ、バイポーラ素子と０ＭＯ８素子とを具備する従
来のＢｉ−ＣＭＯＳ半導体集積回路装置の断面図を示す
。FIG. 2 shows a cross-sectional view of a conventional Bi-CMOS semiconductor integrated circuit device comprising an n-type epitaxial layer V formed on a P-type substrate, a bipolar element, and an OMO8 element.
バイポーラトランジスタ領域とＰチャンネルＭＯ８電界
効果トランジスタ領域、及びバイポーラトランジスタ領
域とバイポーラトランジスタ領域の分離は、Ｐ型基板１
０上に形成されたＰ 型埋め込み層１２と、ｎ型エピタ
キシャル層１３内に形成され、底部が前記Ｐ 型埋め込
み層１２に接触するＰ型ウェル１４と、仙紀ｎ型エピタ
キシマル層１３表面に選択的に形成されたフィールド酸
化膜１６とから構成されている。な訃、図中、１１はＮ
型埋め込み層、１８はペース領域、１７はコレクタ領
域、１９はエミッタ領域、２０はゲート電極、２１はゲ
ート酸化膜、２２及び２３はｎチャンネルＭＱＳ電界効
果トランジスタのソース領域及びドレイン領域、２４及
び２５はＰチャンネルＭＯ８ｉＩＺ界効果トランジスタ
のソース領域及びドレイン領域、２６は酸化膜である。The bipolar transistor region and the P-channel MO8 field effect transistor region and the separation between the bipolar transistor region and the bipolar transistor region are separated by a P-type substrate 1.
0, a P-type well 14 formed in the n-type epitaxial layer 13 and whose bottom is in contact with the P-type buried layer 12, and a P-type well 14 formed on the surface of the Senki n-type epitaxial layer 13. It is composed of a selectively formed field oxide film 16. In the diagram, 11 is N
Type buried layer, 18 is a space region, 17 is a collector region, 19 is an emitter region, 20 is a gate electrode, 21 is a gate oxide film, 22 and 23 are source and drain regions of an n-channel MQS field effect transistor, 24 and 25 are a source region and a drain region of a P-channel MO8iIZ field effect transistor, and 26 is an oxide film.
しかしながら、前述の従来のＢｉ−ＣＭＯ８半導体集積
回路装置の構成によれば、素子間分離領域にＰ型ウェル
１４を用いる必要がある。However, according to the configuration of the conventional Bi-CMO8 semiconductor integrated circuit device described above, it is necessary to use the P-type well 14 in the element isolation region.
ところが、前記ｐ４タエル１４を形成する際には、％温
長時間熱処理による引伸し拡散工程が必要であるために
、この工程におけるウェルの横方向拡散長を考慮すると
、素子分ｉ＠を狭くすることが困難であり、素子の高集
積化の障害となるという欠点がある。However, when forming the p4 taper 14, an elongation diffusion process using a long-term heat treatment at % temperature is required, and therefore, considering the lateral diffusion length of the well in this process, it is necessary to narrow the element portion i@. This has the drawback that it is difficult to implement and becomes an obstacle to high integration of devices.
そこで、本発明はこのような問題点を解決するもので、
その目的とするところは、Ｂｉ−ＣＭＯ８半導体集積回
路装置の機能を妨げることなく、素子分離特性に優れ、
かつ素子の占有面積を減少して素子の集積波を著しく向
上させた半導体集積回路装置を提供するところにある。Therefore, the present invention aims to solve these problems.
The purpose is to achieve excellent element isolation characteristics without interfering with the functionality of the Bi-CMO8 semiconductor integrated circuit device.
Another object of the present invention is to provide a semiconductor integrated circuit device in which the area occupied by the elements is reduced and the integrated wave of the elements is significantly improved.
本発明の半導体集積回路装置は、単一基板上にバイポー
ラ素子と０ＭＯ８素子とを具備する半導体乗積回路装置
において、素子間分離領域が、第１４電型の基板内に形
成された第１４を型の第１半導体領域と、前記基板表面
に形成された第２導電型の半導体層内に形成され底部が
前記第１半導体領域に接触する第１導電型の第２半導体
領域と、前記手導体層衆面の前記第２半導体領域上に選
択的に形成された絶縁襖とからなることを特徴とする。The semiconductor integrated circuit device of the present invention is a semiconductor multiplication circuit device comprising a bipolar element and an 0MO8 element on a single substrate, in which the inter-element isolation region has a fourteenth electrode formed in a substrate of a fourteenth electric type. a first semiconductor region of the mold, a second semiconductor region of the first conductivity type formed in a semiconductor layer of the second conductivity type formed on the surface of the substrate and whose bottom portion contacts the first semiconductor region, and the hand conductor. and an insulating sliding door selectively formed on the second semiconductor region in the general plane.
この場合、前記第２半導体領域が、０ＭＯ８素子が形成
される第１導電型のウェルの周囲に形成されるｌ１ｉｉ
ｔ型のチャンネル・ストッパ領域と同一の工程により形
成された半導体領域であることが好ましい。In this case, the second semiconductor region is formed around the first conductivity type well in which the 0MO8 element is formed.
Preferably, the semiconductor region is formed by the same process as the T-type channel stopper region.
以下、本発明の代表的な実施例を図ｔｈｉを参照して説
明する。Hereinafter, a typical embodiment of the present invention will be described with reference to FIG.
なお、１面において同一あるいは相当する部分は同一符
号で示す。Note that the same or corresponding parts on one side are indicated by the same reference numerals.
第１図は本発明による半導体集積回路装置の−実適例の
断面図をボす。FIG. 1 shows a sectional view of a practical example of a semiconductor integrated circuit device according to the present invention.
第１図に示す半導体集積回路装置は、バイポーラトラン
ジスタＱｂとｎチャネル型ＭＱ８１１Ｌ界効果トランジ
スタＱｎとＰチャネル型ＭＯ８１１界効果トランジスタ
Ｑｐとが同一のＰ型基板１０上に混在して形成されてい
る。The semiconductor integrated circuit device shown in FIG. 1 has a bipolar transistor Qb, an n-channel type MQ811L field effect transistor Qn, and a P-channel type MO811 field effect transistor Qp mixedly formed on the same P-type substrate 10.
第１図において、バイポーラトランジスタＱｂはｎｕｎ
型であってｎ型エピタキシャル層１３に形成されている
。ｎ型エピタキシャル層１３はコレクタ領域をなし、そ
の下にはｎ 型埋め込み層１１が形成されている。この
ｎ型エピタキシャル層１３にＰ型ベース領域１８が形成
され、さらにこのベース領域１８にｎ 型エミッタ領域
１９が形成されている。また、このｎ型エピタキシャル
層１３の別の部分には、ｎ 埋め込み７−に達するｎ
型コレクタ拡散層１７が拡散されている。In FIG. 1, bipolar transistor Qb is nun
type, and is formed in the n-type epitaxial layer 13. The n-type epitaxial layer 13 forms a collector region, and the n-type buried layer 11 is formed below it. A P type base region 18 is formed in this n type epitaxial layer 13, and an n type emitter region 19 is further formed in this base region 18. Further, in another part of this n-type epitaxial layer 13, there is an n layer that reaches the n buried layer 7-.
The type collector diffusion layer 17 is diffused.
他方、ｎチャネルｕＭｏｓｔ界効果トランジスタＱｎは
Ｐ型ウェル１４に形成されている。Ｐ型ウェル１４の下
にはＰ 型埋め込み１ｄ１２が形成され、さらにこのＰ
型ウェル１４の周囲にｒｉＰ＋型チャネル・ストッパ領
域１５が形成されている。On the other hand, an n-channel uMost field effect transistor Qn is formed in the P-type well 14. A P type buried 1d12 is formed under the P type well 14, and this P type well 1d12 is formed under the P type well 14.
An riP+ type channel stopper region 15 is formed around the type well 14.
また、このＰ型ウェル１４には、ゲート電極２０、ダー
ト酸化膜２１、ｎ＋型ソース領域２２、ｎ＋型ドレイン
領域２３が形成されている。Further, in this P-type well 14, a gate electrode 20, a dirt oxide film 21, an n+ type source region 22, and an n+ type drain region 23 are formed.
さらに、Ｐチャネル型Ｍ Ｑ Ｓ 電界効果トランジス
タＱｐはｎ型エピタキシャル層１３に形成されている。Further, a P-channel type MQS field effect transistor Qp is formed in the n-type epitaxial layer 13.
ｎ５工ピタキシヤル層１３の下にはｎ＋型埋め込み層１
１が形成されている。このｎ型エピタキシャル層１３に
は、ゲート電極２０、ゲート酸化＠２１、Ｐ 型ンース
領域２４、Ｐ 型ドレイン領域２５が形成されている。An n+ type buried layer 1 is under the n5 pitaxial layer 13.
1 is formed. In this n-type epitaxial layer 13, a gate electrode 20, a gate oxide @21, a P-type source region 24, and a P-type drain region 25 are formed.
ところで、バイポーラトランジスタＱｂとＰチャネル型
Ｍ ＯＳ ’１ｉ界効果トランジスタ（ＬＰの分離磯城
Ｑｂｐは、Ｐ 型埋め込み層１２と、このＰ＋型埋め込
み層１２上に形成されたＰ 型チャネルストッパ領域１
５と、フィールド酸化膜１６とから構成されている。こ
の構造は、ｎチャネル型電界効果トランジスタＱｎとｐ
ｆ−ｆネル型電界効果トランジスタＱ、ｐの分離領域Ｑ
、ｎｐ 及びバイポーラトランジスタ同志の分離領域
（娼１図に図示せず。）にも適用されている。By the way, the bipolar transistor Qb and the P channel type MOS '1i field effect transistor (LP isolation Isoshiro Qbp) are separated by a P type buried layer 12 and a P type channel stopper region 1 formed on this P+ type buried layer 12.
5 and a field oxide film 16. This structure consists of n-channel field effect transistors Qn and p
Separation region Q of f-f channel field effect transistor Q, p
, np and bipolar transistors (not shown in FIG. 1).
ここで注目すべ＠事項は、上記のように、素子分離領域
がＰ 型埋め込み層１２と、この上に形成されたＰ＋型
チャネル・ストッパ領域１５と、フィールド酸化膜１６
とからなる構造によれば、Ｐウェル１４形成工程とは独
立に素子分離領域を形成することができ、ウェルの横方
向拡散長を考慮する必要がなくなるため、素子分離幅を
狭くすることができる◎
ところで、本構造の半導体集積回路においては、素子分
離領域の不純物プロファイルは、Ｐ 型埋め込みｌ１ｉ
ｉ１２形成工程及びＰ 型チャネル・ストッパ領域１５
形成工程において適当に詞整することが可能でめり、こ
れらを最適化することにより素子分離幅を通常のアイン
プレーナ構造のバイポーラ集積回路装置の素子分離幅に
近い値にすることができ、素子の占有面積を大幅に減少
して集積度の高い半導体集積回路を実現ならしめること
ができる。The important points to note here are that, as mentioned above, the element isolation region consists of the P type buried layer 12, the P+ type channel stopper region 15 formed thereon, and the field oxide film 16.
According to this structure, the element isolation region can be formed independently of the P-well 14 formation process, and there is no need to consider the lateral diffusion length of the well, so the element isolation width can be narrowed. ◎ By the way, in the semiconductor integrated circuit of this structure, the impurity profile of the element isolation region is P-type buried l1i
i12 formation step and P type channel stopper region 15
It is possible to arrange the elements appropriately in the formation process, and by optimizing these, the element isolation width can be made close to the element isolation width of a bipolar integrated circuit device with a normal in-planar structure. It is possible to significantly reduce the area occupied by the semiconductor integrated circuit and realize a highly integrated semiconductor integrated circuit.
次に、上記半導体集積回路装置の製造方法を第３図につ
いて１幀次説明する。Next, a method for manufacturing the semiconductor integrated circuit device will be briefly explained with reference to FIG.
（１］ まず、第５図（ａ）は本発明による半導体果
槓回路装ｍｔ−ｎ造するために予備加工された半導体基
板の一部を示す。同図において、Ｐ型半導体基板１０に
はｎ型エピタキシャル層１３が形成され、また基板１０
とエピタキシャル層１３との＋
間にはＰ′ 型埋め込み層１１及びＰ 型埋め込み層１
２が形成されている。なお、Ｐ 型埋め込み７＊１１ｒ
ｉバイポーラ素子及びＰＭＯ８素子に形成される。(1) First, FIG. 5(a) shows a part of a semiconductor substrate that has been preprocessed for manufacturing a semiconductor circuit device mt-n according to the present invention. An n-type epitaxial layer 13 is formed, and a substrate 10
A P'-type buried layer 11 and a P-type buried layer 1 are provided between + and epitaxial layer 13.
2 is formed. In addition, P type embedding 7*11r
It is formed into an i bipolar element and a PMO8 element.
（２）次に、第３図（１））は前記半導体基板にＰ型ウ
ェル１４を形成した状帽を示す。ＰＷウェル１４はＮＭ
Ｏ８素子領域のＰ 型埋め込み１ｊｌＺ上に形成される
。(2) Next, FIG. 3 (1)) shows a cap in which a P-type well 14 is formed in the semiconductor substrate. PW well 14 is NM
It is formed on the P type buried 1jlZ in the O8 element region.
（３） さらに、第３図（Ｃ）は前記半導体基板にＰ
型チャネル・ストッパ領域１５を形成した状叩を示す
。このＰ 型チャネルｅストッパ領域１５は、イオン打
込みとその後の引伸し拡散とにより、Ｐ型ウェル１４の
周囲及び素子分離領域に形成される。なお、図中２６は
酸化膜、２７は窒化膜である。この窒化膜２７は素子形
成領域に選択的に形成される。(3) Furthermore, FIG. 3(C) shows that P is applied to the semiconductor substrate.
Figure 3 shows the punch forming the mold channel stopper region 15; This P type channel e-stopper region 15 is formed around the P type well 14 and in the element isolation region by ion implantation and subsequent stretching diffusion. In the figure, 26 is an oxide film, and 27 is a nitride film. This nitride film 27 is selectively formed in the element formation region.
（４）１３図（ｄ）は、前記半導体基板にＴ、０−ａＯ
Ｓによる厚いフィールド酸化膜１６を形成した状態を示
す。このフィールド酸化膜１６は素子形成領域以外の部
分に形成される。(4) Figure 13(d) shows that the semiconductor substrate has T, 0-aO
A state in which a thick field oxide film 16 made of S is formed is shown. This field oxide film 16 is formed in a portion other than the element formation region.
以下、従来の半導体集積回路装置の製造方法シて従うこ
とにより、前述した如き効果を奏する半導体集積回路が
比較的少ない工程で形成される。Hereinafter, by following the conventional manufacturing method of a semiconductor integrated circuit device, a semiconductor integrated circuit having the above-mentioned effects can be formed in a relatively small number of steps.
以上本発明を実施例にもとでいて具体的に説明してきた
が、本発明は本実施例に限定されず、その要旨を逸脱し
ない範囲で徨々変更可能であること１１言うまでもない
。Although the present invention has been specifically explained above based on examples, it goes without saying that the present invention is not limited to these examples and can be modified at will without departing from the gist thereof.
以上述べたように、本発明の半導体集積回路装置によれ
ば、素子分離領域を埋め込み層とチャネル・ストッパ領
域と選択絶縁膜からなる構造とすることにより、素子分
離＠を大幅に狭くすることかで′＠る。その結果、素子
の占有面積を低減できるため、著しい高密度化が達成で
きる。As described above, according to the semiconductor integrated circuit device of the present invention, by forming the element isolation region into a structure consisting of a buried layer, a channel stopper region, and a selective insulating film, the element isolation @ can be significantly narrowed. Out. As a result, it is possible to reduce the area occupied by the elements, thereby achieving a significant increase in density.
また、分離領域の不純物プロファイルは埋め込み層形成
工程及びチャネル・ストッパ領域形成工程において調整
して最適化することができ、素子間リークのない素子分
離特性に優れる等の効果を有する。Further, the impurity profile of the isolation region can be adjusted and optimized in the buried layer forming process and the channel/stopper region forming process, and has effects such as excellent element isolation characteristics without inter-element leakage.
以上の説明では主として本発明をその背景となった利用
分野であるＢｉ−ＣＭＯ８半導体集積回路装置に適用し
た場合について述べたが、それに限定されるものではな
く、例えばＣ！ＭＯＥ＋半導体集積回路装置もしくはバ
イポーラ半導体集積回路等にも適用可能である。In the above description, the present invention was mainly applied to a Bi-CMO8 semiconductor integrated circuit device, which is the background field of application, but the present invention is not limited thereto. It is also applicable to MOE+ semiconductor integrated circuit devices, bipolar semiconductor integrated circuits, etc.
第１図は本発明の半導体集積回路装置の一実施例を示す
断面図、
第２図は従来の半導体集積回路装置を示す断面図、
第３図（ａ）〜（ｄ）は本発明の実施例を示す半導体集
積回路装置の製造工程断面図である。
１０・・・・・・Ｐ型半導体基板
１２・・・・・・Ｐ 型埋め込み層
１５・・・・・・Ｐ 型チャネル・ストッパ領域１６・
・・・・・フィールド酸化膜
板 上
出願人 セイコーエプソン株式会社
第 ｌ 図
１と
儲 ２ 図
（ａ）
ＣＩ））
（Ｃ）
箋３図FIG. 1 is a sectional view showing an embodiment of a semiconductor integrated circuit device of the present invention, FIG. 2 is a sectional view showing a conventional semiconductor integrated circuit device, and FIGS. 3(a) to (d) are embodiments of the present invention. FIG. 3 is a cross-sectional view of a manufacturing process of a semiconductor integrated circuit device showing an example. 10... P-type semiconductor substrate 12... P-type buried layer 15... P-type channel stopper region 16...
...Field oxide film plate Applicant: Seiko Epson Corporation No. 1 Figure 1 and Figure 2 (a) CI)) (C) Notebook Figure 3
Claims (2)
具備する半導体集積回路装置において、素子間分離領域
が、第１導電型の基板内に形成された第１導電型の第１
半導体領域と、前記基板表面に形成された第２導電型の
半導体層内に形成され底部が前記第１半導体領域に接触
する第１導電型の第２半導体領域と、前記半導体層表面
の前記第２半導体領域上に選択的に形成された絶縁膜と
からなることを特徴とする半導体集積回路装置。(1) In a semiconductor integrated circuit device including a bipolar element and a CMOS element on a single substrate, an inter-element isolation region is formed in a first conductivity type substrate.
a semiconductor region, a second semiconductor region of a first conductivity type formed in a semiconductor layer of a second conductivity type formed on the surface of the substrate and whose bottom portion contacts the first semiconductor region; 1. A semiconductor integrated circuit device comprising: 2 an insulating film selectively formed on a semiconductor region.
る第１導電型のウェルの周囲に形成される第１導電型の
チャンネル・ストッパ領域と同一の工程により形成され
た半導体領域であることを特徴とする特許請求の範囲第
１項記載の半導体集積回路装置。(2) The second semiconductor region is a semiconductor region formed by the same process as a first conductivity type channel stopper region formed around a first conductivity type well in which a CMOS element is formed. A semiconductor integrated circuit device according to claim 1, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61278191A JP2600151B2 (en) | 1986-11-21 | 1986-11-21 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61278191A JP2600151B2 (en) | 1986-11-21 | 1986-11-21 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63131562A true JPS63131562A (en) | 1988-06-03 |
| JP2600151B2 JP2600151B2 (en) | 1997-04-16 |
Family
ID=17593859
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61278191A Expired - Lifetime JP2600151B2 (en) | 1986-11-21 | 1986-11-21 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2600151B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5081515A (en) * | 1989-03-20 | 1992-01-14 | Hitachi, Ltd. | Semiconductor integrated circuit device |
| US5920107A (en) * | 1996-04-25 | 1999-07-06 | Nec Corporation | Semiconductor integrated circuit device with high integration density |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60109262A (en) * | 1983-11-18 | 1985-06-14 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS61212054A (en) * | 1985-03-18 | 1986-09-20 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS61214557A (en) * | 1985-03-20 | 1986-09-24 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
-
1986
- 1986-11-21 JP JP61278191A patent/JP2600151B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60109262A (en) * | 1983-11-18 | 1985-06-14 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS61212054A (en) * | 1985-03-18 | 1986-09-20 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS61214557A (en) * | 1985-03-20 | 1986-09-24 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5081515A (en) * | 1989-03-20 | 1992-01-14 | Hitachi, Ltd. | Semiconductor integrated circuit device |
| US5920107A (en) * | 1996-04-25 | 1999-07-06 | Nec Corporation | Semiconductor integrated circuit device with high integration density |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2600151B2 (en) | 1997-04-16 |
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