JPH08139198A - Semiconductor device - Google Patents

Abstract

PURPOSE: To provide excellent insulation between transistors as compared with a conventional well structure, to improve the withstand voltage of the transistor and to suppress the latchup by providing an insular region including an insulating part, i.e., a well region in a specific conductivity type semiconductor substrate. CONSTITUTION: An insular insulating region 102 is provided on an N-type semiconductor substrate 101, and further an insular P-type region 103 is provided in the region 102. An N-type region 104 to become source and drain regions is provided in the region 103. A thin gate oxide film 105 is provided between the regions 104, and a thick field oxide film 106 is provided on the other surface. The film 106 has an opening on the region 104, and a source electrode 107 and a drain electrode 108 are provided here. Further, a gate electrode 109 is installed at the specific part of the film 105.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a MOS (Metal Oxide Semiconductor) integrated circuit device, in particular to a structure related to a well, and a manufacturing method thereof.

[0002]

2. Description of the Related Art In a CMOS transistor, since both an NMOS transistor and a PMOS transistor need to be formed on the same substrate, it is necessary to form at least a region of a conductivity type opposite to that of a semiconductor substrate. Such a region is called a well.

In the case of a CMOS transistor, a method of forming an N-type well on a P-type semiconductor substrate, a method of forming a P-type well on an N-type semiconductor substrate, a P-type well and an N-type on a P-type or N-type semiconductor substrate. There is a method of forming both of the wells, and which of those configurations is used depends on the device to be manufactured.

CMOS transistors have problems such as a latch-up phenomenon due to the generation of parasitic transistors and malfunctions due to α-rays, which are a major problem when applied to memories and the like. Has been done to.

However, with the recent increase in the degree of integration of semiconductors,
The above problems are becoming more and more serious, and further solutions are required. In view of the above problems, the present invention provides various methods for solving the problems.

Some of the typical solutions to the above problems are shown below from the patent publications and the like, and the respective problems are also described.

JP-A-60-124863: This is related to FIGS. 1 and 2 which will be described later, in which the well structure is a double vertical stack structure so as to suppress the interference between the wells. However, this causes a problem that the parasitic capacitance between the wells becomes too large, which hinders high-speed operation.

Japanese Unexamined Patent Publication No. 60-154663: This relates to FIGS. 3 and 4 which will be described later. The well concentration around the drain is made thinner than the other well portions, but the well around the drain is simply There is a problem that the latch-up phenomenon is not sufficiently suppressed because only the concentration is reduced.

Japanese Unexamined Patent Publication No. 61-268058: This is related to FIGS. 5 and 6 which will be described later, and is intended to reduce the latch-up phenomenon by providing an impurity concentration gradient in the well. However, this causes a problem that the parasitic capacitance between the wells becomes too large, which hinders high-speed operation.

JP-A-61-2222251: This is related to FIG. 7, which will be described later, in which a low resistance region is provided in the well region. There has been a problem that the current flowing becomes large and the total power consumption becomes too large.

Japanese Unexamined Patent Publication No. 62-54466: This relates to FIG. 8 to be described later, which forms an impurity region for suppressing the substrate current in the lower portion of the channel region at a deep portion, but forms the structure. It has a problem that the process is complicated.

JP-A-1-276662, JP-A-60-
65562: This relates to FIG. 9 to be described later, in which wells having different depths are formed on the same substrate, but the mask for forming such a structure becomes complicated. Had a point.

Japanese Unexamined Patent Publication No. 2-214114: This relates to FIG. 10, which will be described later, in which a well is formed by using high energy channeling ion implantation after forming an element isolation film. Had a problem that it could not be sufficiently reduced.

JP-B-61-55250, JP-B-3-12
475, JP-A-56-62333, and JP-A-58-111.
345, Japanese Patent Laid-Open No. 59-231833: This is related to FIG. 10 described later, and as a method of forming an insulating region inside the substrate under the element portion, heat treatment after ion implantation of oxygen or nitrogen ions is performed. To react with the substrate material, silicon, to form an insulating region. However, if the parasitic capacitance is to be made sufficiently small, a considerable amount of ions need to be implanted, so that the manufacturing time becomes too long, and a material that chemically reacts with the substrate is ion-implanted. There is a problem that the remaining material adversely affects the device characteristics.

[0015]

SUMMARY OF THE INVENTION The present invention provides a measure for solving the above-mentioned problems relating to wells, and its purpose is to provide better insulation between transistors than the conventional well structure and A method of improving the breakdown voltage of the transistor, suppressing the latch-up phenomenon, stabilizing the well potential, reducing the junction capacitance of the well, and providing a method of mixing a high breakdown voltage element and a low breakdown voltage element with a structure that can be miniaturized. It is a thing.

[0016]

A semiconductor device according to the present invention is characterized by having an island-shaped region including an insulating portion, that is, a well region, in a semiconductor substrate of a specific conductivity type. By controlling in which region of the well the insulating portion is installed, the electrical characteristics of the well can be controlled in various ways, and the electrical characteristics and integration of the device can be freely controlled according to the purpose.

Specifically, a heavy metal is selectively introduced into an appropriate place in the substrate by using a technique such as ion implantation to increase the resistance, or a designated portion is formed by using a non-doped substrate to which impurities are not added in advance. The structure is formed by covering it with a resist or the like and leaving it undoped even after performing a treatment such as ion implantation.

[0018]

1 is a sectional view of a MOS integrated circuit according to an embodiment of a semiconductor device of the present invention.

In this structure, the N-type semiconductor substrate 101 has an island-shaped insulating region 102, and the island-shaped insulating region 10 is further provided.
2 has an island-shaped P-type region 103. The island-shaped P-type region 103 has an N-type region 104 serving as a source region and a drain region. A thin gate oxide film 105 is provided between the N-type regions 104, and a thick field oxide film 106 is provided on the other surface. The field oxide film 106 has an opening on the N-type region 104, where the source electrode 10 is formed.
7 and a drain electrode 108 are provided. Further, a gate electrode 109 is provided on a specific portion of the gate oxide film 105.

The island-shaped insulating region 102 can be easily formed by covering a region other than the place where the island-shaped insulating region 102 is formed with a mask material such as a resist and ion-implanting a heavy metal. As the heavy metal, a material that forms a deep level in the substrate material is used. For example, when a silicon substrate is used, materials such as iron, gold and copper can be used, and when a gallium arsenide substrate is used, materials such as chromium and iron can be used. A material that forms a deep level causes its effect with a small amount of injection, that is, insulation of the material, and unlike oxides, etc., it does not reach perfect insulation, and a small number of carriers cause a slight leak. The feature is that there is.

As described above, each MOS transistor is completely separated from the others by the island-shaped insulating region 102.
The interference between the S transistors can be sufficiently removed. Therefore, such an effect is very large in that good analog characteristics can be obtained by the structure in which the cross-sectional structure of the MOS transistor is separated by the island-shaped insulating region.

FIG. 2 is a sectional view of a MOS integrated circuit according to an embodiment of the semiconductor device of the present invention.

In this structure, the non-doped semiconductor substrate 20 is used.
1 has an island-shaped P-type region 202. The N-type region 2 serving as a source region and a drain region is formed on the island-shaped P-type region 202.
Has 03. A thin gate oxide film 204 is provided between the N-type regions 203, and a thick field oxide film 205 is provided on the other surface. The field oxide film 205 is N
The source electrode 20 has an opening on the mold region 203.
6, a drain electrode 207 is provided. Further, a gate electrode 208 is provided on a specific portion of the gate oxide film 204.

As described above, each MOS transistor is completely separated from the others by the insulating non-doped semiconductor substrate 201, and the interference between the MOS transistors can be sufficiently eliminated. Therefore, the effect is very large in that good analog characteristics can be obtained by the structure in which the cross-sectional structure of the MOS transistor is separated by the insulating substrate.

FIG. 3 is a sectional view of a MOS integrated circuit according to an embodiment of the semiconductor device of the present invention.

In this structure, the N-type semiconductor substrate 301 has an island-shaped P-type region 302, and the island-shaped P-type region 30 is further provided.
2 is an N-type region 303 serving as a source region and a drain region.
have. The N-type region 303 has an insulating island region 304 below the drain region. The insulating island region 304 needs to have the same size as or larger than the N-type region 303. However, it is desirable that the sizes are the same from the viewpoint of the number of masks. However, empirically, it has been found that the larger the effect that can be obtained, the larger the effect that can be obtained without eroding other areas. A thin gate oxide film 305 is provided between the N-type regions 303, and a thick field oxide film 306 is provided on the other surface. The field oxide film 306 is N
The source electrode 30 has an opening on the mold region 303.
7, a drain electrode 308 is provided. Further, a gate electrode 309 is provided on a specific portion of the gate oxide film 305.

Here, in the insulating island-shaped region 304 below the drain region, the island-shaped P-type region 302 is formed by a usual method, and then a heavy metal is ion-implanted at an appropriate position using a mask material such as a resist. It can be easily formed by things such as.

By thus increasing the resistance of the lower part of the drain of the MOS transistor, the insulating property of the drain end is improved,
The breakdown voltage of the transistor can be improved. Therefore, by increasing the resistance of the drain lower region of the MOS transistor in this way, the withstand voltage of the MOS transistor can be improved, and the effect is very large.

FIG. 4 is a sectional view of a MOS integrated circuit according to an embodiment of the semiconductor device of the present invention.

In this structure, the non-doped semiconductor substrate 40
1 has an island-shaped P-type region 402, and further has an N-type region 403 serving as a source region and a drain region in this island-shaped P-type region 402. An insulating island region 404 is provided around the drain region. A thin gate oxide film 405 is provided between the N-type regions 403, and a thick field oxide film 406 is provided on the other surface. The field oxide film 406 has an opening on the N-type region 403, and a source electrode 407 and a drain electrode 408 are provided therein. Further, the gate electrode 4 is formed on a specific portion of the gate oxide film 405.
09 is installed.

Here, the insulating island-shaped region 404 around the drain region is covered with a mask material such as a resist when forming the island-shaped P-type region 402, and is left undoped. It can be easily formed. When this method is adopted, the breakdown voltage at the drain end can be determined by how much the depletion layer that spreads according to the voltage applied to the drain spreads to the non-doped region, and when designing a high breakdown voltage transistor, This method is easy to adopt. Needless to say, the structure in which the non-doped region is provided only in the lower portion of the drain as shown in FIG. 3 may be used instead of surrounding the region of the island P-type region in contact with the drain.

By thus providing the non-doped region around the drain of the MOS transistor, the electric field gradient at the drain end becomes gentle and the breakdown voltage of the transistor can be improved. Therefore, by increasing the resistance of the drain peripheral region of the MOS transistor in this manner, the breakdown voltage of the MOS transistor can be improved.
The effect is very large.

FIG. 5 is a sectional view of a MOS integrated circuit according to an embodiment of the semiconductor device of the present invention.

In this structure, the N-type semiconductor substrate 501 has an island-shaped P-type region 502, and the island-shaped P-type region 50 is further provided.
2 is an N-type region 503 serving as a source region and a drain region.
have. An insulating island region 504 is provided below the source and drain regions. A thin gate oxide film 505 is provided between the N-type regions 503, and a thick field oxide film 506 is provided on the other surface. The field oxide film 506 has an opening on the N-type region 503, and a source electrode 507 and a drain electrode 508 are provided therein. Further, a gate electrode 509 is provided on a specific portion of the gate oxide film 505.

Here, the insulating island region 504 under the source and drain regions is formed in the island P-type region 50 by a usual method.
After forming 2, the mask can be easily formed by ion-implanting a heavy metal at an appropriate position using a mask material such as a resist.

By thus providing the high resistance region under the source and drain of the MOS transistor, the latch-up breakdown voltage of the transistor can be improved. Therefore, by increasing the resistance of the source and drain lower regions of the MOS transistor in this manner, the latch-up breakdown voltage of the MOS transistor can be improved, which is very effective.

FIG. 6 is a sectional view of a MOS integrated circuit according to an embodiment of the semiconductor device of the present invention.

In this structure, the non-doped semiconductor substrate 60 is used.
1 has an island-shaped P-type region 602, and further has an N-type region 603 serving as a source region and a drain region in this island-shaped P-type region 602. An insulating island region 604 is provided below the source and drain regions. N-type region 60
3 has a thin gate oxide film 605, but has a thick field oxide film 606 on the other surface. The field oxide film 606 has an opening on the N-type region 603, and a source electrode 607 and a drain electrode 608 are provided therein. Further, a gate electrode 609 is provided on a specific portion of the gate oxide film 605.

Here, the insulating island regions 604 under the source and drain regions should be left undoped by covering appropriate positions with a mask material such as a resist when forming the island P-type regions 602. It can be easily formed by, for example. The insulating island region 604 under the formed source / drain regions may be formed to a depth of about 0.5 μm to 1.0 μm.

By thus providing the high resistance region under the source and drain of the MOS transistor, the latch-up breakdown voltage of the transistor can be improved. Therefore, by increasing the resistance of the source and drain lower regions of the MOS transistor in this manner, the latch-up breakdown voltage of the MOS transistor can be improved, which is very effective.

FIG. 7 is a sectional view of a MOS integrated circuit according to an embodiment of the semiconductor device of the present invention.

In this structure, the N-type semiconductor substrate 701 has an island-shaped P-type region 702, and the island-shaped P-type region 70 is further provided.
N-type region 703 serving as a source region and a drain region
have. An insulating region 704 is provided below the island-shaped P-type region 702. A thin gate oxide film 705 is provided between the N-type regions 703, and a thick field oxide film 706 is provided on the other surface. Field oxide film 7
06 has an opening on the N-type region 703, and a source electrode 707 and a drain electrode 708 are provided therein. Further, the gate electrode 70 is formed on a specific portion of the gate oxide film 705.
9 are installed.

Here, the insulating region 704 below the island-shaped P-type region 702 is formed of a heavy metal by using a mask material such as a resist before or after the island-shaped P-type region 702 is formed by a usual method. It can be easily formed by implanting ions at appropriate positions.

By thus providing the high resistance region below the island-shaped region including the MOS transistor, the latch-up breakdown voltage of the transistor can be improved. Therefore, by increasing the resistance of the lower region of the island-shaped region including the MOS transistor in this manner, the latch-up breakdown voltage of the MOS transistor can be improved, which is very effective.

FIG. 8 is a sectional view of a MOS integrated circuit according to an embodiment of the semiconductor device of the present invention.

In this structure, the non-doped semiconductor substrate 80
1 has an island-shaped P-type region 802, and further has an N-type region 803 serving as a source region and a drain region in this island-shaped P-type region 802. An insulating region 804 is provided below the channel portion of the island-shaped P-type region 802. A thin gate oxide film 805 is provided between the N-type regions 803, and a thick field oxide film 806 is provided on the other surface. The field oxide film 806 has an opening on the N-type region 803, and a source electrode 807 and a drain electrode 808 are provided therein. Further, a gate electrode 809 is provided on a specific portion of the gate oxide film 805.

The insulating region 804 below the channel portion is
When the island-shaped P-type region 802 is formed, it can be easily formed by covering an appropriate position with a mask material such as a resist and leaving it undoped.

As described above, by providing the high resistance region under the channel portion of the MOS transistor, the latch-up breakdown voltage of the transistor can be improved. Therefore, by increasing the resistance of the lower region of the channel portion of the MOS transistor in this manner, the latch-up breakdown voltage of the MOS transistor can be improved, which is very effective.

FIG. 9 is a sectional view of a MOS integrated circuit according to an embodiment of the semiconductor device of the present invention.

In this structure, an N-type semiconductor substrate 901 has an island-shaped P-type region 902, and the island-shaped P-type region 90 is further provided.
N-type region 903 serving as a source region and a drain region in FIG.
have. Below the island-shaped P-type region 902, those having an insulating region 904 and those not having the insulating region 904, and those having a different film thickness of the region are installed. N-type region 90
3 has a thin gate oxide film 905, but has a thick field oxide film 906 on the other surface. The field oxide film 906 has an opening on the N-type region 903, and a source electrode 907 and a drain electrode 908 are provided therein. Further, a gate electrode 909 is provided on a specific portion of the gate oxide film 905.

Here, in the insulating region 904 below the island-shaped P-type region 902, after the island-shaped P-type region 902 is formed by a usual method, a heavy metal is placed at an appropriate position by using a mask material such as a resist. It can be easily formed by implanting ions. A structural region that functions as a well to be formed,
That is, the thickness of the structure which does not include the lower insulating region 904 in the island-shaped P-type region 902 can usually be selected in the range of about 0.5 μm to 5 μm.

Since the high resistance regions having different film thicknesses are provided below the channel portion of the MOS transistor in this way, the well structures having different depths are formed below the transistor structure portion. Pressure resistance of
The degree of aggregability can be controlled. Therefore, by increasing the resistance of the lower region of the channel portion of the MOS transistor with various film thicknesses as described above, it is possible to form MOS transistors having different characteristics on the same substrate. large.

FIG. 10 is a sectional view of a MOS integrated circuit according to an embodiment of the semiconductor device of the present invention.

In this structure, the N-type semiconductor substrate 1001 has the element isolation oxide film 1002, and the island-shaped P-type region 1003.
There is an insulating region 1004 below the island-shaped P-type region 1003. Furthermore, this island-shaped P-type region 1003
N-type region 1005 which becomes a source region and a drain region
have. A thin gate oxide film 1006 is provided between the N-type regions 1005. A source electrode 1007 and a drain electrode 1008 are provided on the N-type region 1005. Further, a gate electrode 1009 is provided on a specific portion of the gate oxide film 1006.

Here, the insulating region 1004 below the island-shaped P-type region 1003 is formed with the island-shaped P-type region 1003 by a method called a normal locos through, and then a heavy metal is placed at an appropriate position by the same method. It can be easily formed by implanting ions. Unlike the silicon dioxide formed by oxidizing silicon, the insulating region 1004 formed in this manner has a slight conductivity because a small number of carriers function, and therefore has a conventional conductivity. It has a feature that it does not have a parasitic capacitance component unlike the insulation method using silicon. Therefore, this embodiment can be a particularly effective method when manufacturing a high-speed operation device.

By thus providing the high resistance region below the island-shaped region including the MOS transistor, the latch-up breakdown voltage of the transistor can be improved, and the junction capacitance between the source / drain region and the well can be improved. Can be reduced. Therefore, by increasing the resistance of the lower region of the island-shaped region including the MOS transistor as described above, the latch-up breakdown voltage of the MOS transistor can be improved and the speed can be increased, which is a great effect.

It should be noted that, although the above-described embodiments have been shown only for the NMOS type, it is clear that the PMOS type can also be realized by using a similar method, and those are also within the scope of the present invention. Further, as a method for increasing the resistance of a certain region, a method of ion-implanting a heavy metal was adopted as an example, but it is clear that the same effect can be obtained by using other methods.

[0058]

By using the semiconductor device of the present invention, the conventional well-related problem, that is, C
For the latch-up phenomenon due to the generation of parasitic transistors found in MOS transistors, malfunctions due to α rays, which is a major problem when applied to memories, etc.,
It was possible to obtain even better characteristics than before.

[Brief description of drawings]

FIG. 1 is an MO according to an embodiment of a semiconductor device according to the present invention.
Sectional drawing of an S integrated circuit.

FIG. 2 is an MO according to one embodiment of a semiconductor device according to the present invention.
Sectional drawing of an S integrated circuit.

FIG. 3 is an MO according to one embodiment of a semiconductor device according to the present invention.
Sectional drawing of an S integrated circuit.

FIG. 4 is an MO according to one embodiment of a semiconductor device according to the present invention.
Sectional drawing of an S integrated circuit.

FIG. 5 is an MO according to one embodiment of a semiconductor device according to the present invention.
Sectional drawing of an S integrated circuit.

FIG. 6 is an MO according to one embodiment of a semiconductor device according to the present invention.
Sectional drawing of an S integrated circuit.

FIG. 7 shows an MO according to one embodiment of a semiconductor device according to the present invention.
Sectional drawing of an S integrated circuit.

FIG. 8 is an MO according to one embodiment of a semiconductor device according to the present invention.
Sectional drawing of an S integrated circuit.

FIG. 9 is an MO according to one embodiment of a semiconductor device according to the present invention.
Sectional drawing of an S integrated circuit.

FIG. 10 shows an M according to one embodiment of a semiconductor device according to the present invention.
FIG. 3 is a cross-sectional view of an OS integrated circuit.

[Explanation of symbols]

 101 N-type semiconductor substrate 102 Island-shaped insulating region 103 Island-shaped P-type region 104 N-type region serving as a source region and a drain region 105 Gate oxide film 106 Field oxide film 107 Source electrode 108 Drain electrode 109 Gate electrode 201 Non-doped semiconductor substrate 202 Island P-type region 203 N-type region serving as a source region and a drain region 204 Gate oxide film 205 Field oxide film 206 Source electrode 207 Drain electrode 208 Gate electrode 301 N-type semiconductor substrate 302 Island-shaped P-type region 303 Source region and drain region N-type region 304 Insulating island region 305 Gate oxide film 306 Field oxide film 307 Source electrode 308 Drain electrode 309 Gate electrode 401 Non-doped semiconductor substrate 402 Island P-type region 403 Source region, drain N-type region 404 to be an insulating region 405 Insulating island region 405 Gate oxide film 406 Field oxide film 407 Source electrode 408 Drain electrode 409 Gate electrode 501 N-type semiconductor substrate 502 Island P-type region 503 Source and drain regions N-type region 504 Insulating island region 505 Gate oxide film 506 Field oxide film 507 Source electrode 508 Drain electrode 509 Gate electrode 601 Non-doped semiconductor substrate 602 Island P-type region 603 N-type region serving as source region and drain region 604 Insulation Island region 605 gate oxide film 606 field oxide film 607 source electrode 608 drain electrode 609 gate electrode 701 N-type semiconductor substrate 702 island P-type region 703 N-type region to be a source region and a drain region 704 insulating region 05 Gate Oxide Film 706 Field Oxide Film 707 Source Electrode 708 Drain Electrode 709 Gate Electrode 801 Non-Doped Semiconductor Substrate 802 Island P-type Region 803 Source and Drain Region N-type Region 804 Insulating Region 805 Gate Oxide 806 Field Oxidation Film 807 Source electrode 808 Drain electrode 809 Gate electrode 901 N-type semiconductor substrate 902 Island P-type region 903 Source region, N-type region serving as drain region 904 Insulating region 905 Gate oxide film 906 Field oxide film 907 Source electrode 908 Drain Electrode 909 Gate electrode 1001 N-type semiconductor substrate 1002 Element isolation oxide film 1003 Island-shaped P-type region 1004 Insulating region 1005 N-type region serving as a source region and a drain region 1006 Gate oxide film 1 07 source electrode 1008 drain electrode 1009 gate electrode

Claims (8)

[Claims] 1. A semiconductor substrate of a specific conductivity type is provided with an insulating island region formed by mixing a heavy metal, and the insulating island region is of the same conductivity type as or opposite to the specific conductivity type. A second island-shaped region is provided, and a MOS is formed in the second island-shaped region.
A semiconductor device having a transistor formed therein. 2. A non-doped semiconductor substrate is used as a starting material, a second island-shaped region which is the same as or different from the specific conductivity type is provided in a region of the specific conductivity type, and a MOS transistor formed in the island-shaped region is formed. A semiconductor device, characterized in that the region around the drain region is an insulating material with the starting material as it is. 3. A second island region, which is the same as or different from the specific conductivity type, is provided in a semiconductor substrate of the specific conductivity type, and a source or drain region or both of the source and drain regions of a MOS transistor formed in the island region are provided. A semiconductor device, characterized in that an insulating region formed by mixing a heavy metal is formed in the lower part of the region and in the island region. 4. A non-doped semiconductor substrate is used as a starting material, and a second island region, which is the same as or different from the specific conductivity type, is provided in a region of the specific conductivity type, and the bottom of the island region is the starting material. A semiconductor device having an insulating property. 5. An insulating property in which a second conductive region having the same conductivity type as or different from the conductive region is provided in a semiconductor substrate of a specific conductivity type, and a heavy metal is mixed under a channel forming region of the island region. A semiconductor device having a region. 6. A non-doped semiconductor substrate is used as a starting material, a second conductive region which is the same as or different from the conductive region is provided in a region of a specific conductivity type, and the lower portion of the channel forming region of the island region is the starting material. A semiconductor device having an insulating property. 7. An insulating island-shaped region containing a heavy metal, which is formed by high-energy channeling ion implantation after an element isolation film is formed on a semiconductor substrate of a specific conductivity type. Semiconductor device. 8. A method of ion-implanting iron, gold, copper or the like when a silicon substrate is used and chromium, iron or the like when a gallium arsenide substrate is used as a heavy metal for forming an insulating region. Claim 1, characterized in that
8. The method for manufacturing a semiconductor device according to any one of 3, 5, and 7.