JPH0461377A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To perform a low voltage operation by reducing impurity concentration of the lower part of a channel region of an access transistor lower than that of the lower part of a channel region of a driver transistor. CONSTITUTION:A p-well 2 is formed in a semiconductor substrate 1, a field insulating film 3 like an SiO2 film is selectively formed, elements are isolated therebetween, and an insulating film such as an SiO2 film is formed on an active region surrounded by the film 3 by a thermally oxidizing method. Then, an n-type impurity such as phosphorus is ion implanted at the lower part of a channel region by relatively high energy through the insulating film. Thus, the impurity concentration of the well 2 of the lower part of the channel region is reduced. Thereafter, after the insulating film is removed by etching, a gate insulating film 4 such as an SiO2 film is formed on the active region surrounded by the film 3 by a thermally oxidizing method to complete a MOS static RAM. Thus, a substrate bias effect can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory, and is particularly suitable for application to a MOS static RAM.

[Summary of the invention]

The present invention provides a semiconductor memory in which a memory cell is constituted by a flip-flop circuit consisting of a pair of driver transistors and a pair of loads, and a pair of access transistors. By making the impurity concentration lower than the impurity concentration in the lower part of the region, it is possible to realize a semiconductor memory that can operate at a low voltage.

[Conventional technology]

In recent years, in MO3LSI, as the short channel effect has become more prominent with the progress of miniaturization of MOS transistors, the impurity concentration of the well in which the MOS transistor is formed has been increased in order to prevent this short channel effect. There is. As a result, the substrate bias effect has become so large that it cannot be ignored. For this reason, for example, M
In the OS static RAM, there is a problem in that the threshold voltage (1) and (2) during operation of the access transistor increases, resulting in a decrease in data retention ability.

In other words, the power supply voltage ■ determines the characteristics of MOS static RAM. The minimum value VCCair+ is given by the following equation.

V CCmi,, = (VTM of driver transistor
)+(VTM of access transistor)+ΔVTII The last term in this equation represents the change in VT)I of the access transistor due to the body bias effect. As can be seen from this equation, the greater the substrate bias effect, the greater the
The larger 14, the larger VCCeh4n becomes, and the performance of the MOS static RAM deteriorates.

[Problems to be Solved by the Invention] As described above, the increase in VTN of the access transistor due to the substrate bias effect has led to a decrease in the performance of the MOS static RAM.

Therefore, an object of the present invention is to provide a semiconductor memory that can suppress the increase in the threshold voltage of an access transistor due to the substrate bias effect and realize a semiconductor memory that can operate at a low voltage.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a flip-flop circuit including a pair of driver transistors (Q,,Q,) and a pair of loads, and a pair of access transistors (Q,).
In a semiconductor memory where a memory cell is formed by a driver transistor (Q,), the impurity concentration in the lower part of the channel region of an access transistor (Q,,Q,) is lower than that of a driver transistor (Ql).

Q,) is lower than the impurity concentration at the bottom of the channel region.

r effect] According to the semiconductor memory of the present invention configured as described above, the impurity concentration in the lower part of the channel region of the access transistor (Q, , Q,) is higher than that of the driver transistor (Q, , Q).
Since the impurity concentration is lower than the impurity concentration in the lower part of the channel of the access transistors (Q,,Q,), it is possible to suppress the increase in the threshold voltage of the access transistor (Q,,Q,) due to the substrate bias effect. For this reason, ■Ce1l! 21 can be kept low. This makes it possible to realize a semiconductor memory capable of low voltage operation.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows a standard transistor arrangement within a memory cell of a MOS static RAM.

In FIG. 2, Q, , and Q represent a pair of driver transistors that constitute a memory cell;

Q4 indicates a pair of access transistors forming a memory cell, G, , G are driver transistors Q5, . In addition, WL indicates a word line forming the gate electrodes of access transistors Qz and Q4. In FIG. 2, the region surrounded by dotted lines is the channel region.

In this embodiment, access transistors Qs, Q
The impurity concentration at the bottom of the channel region of driver transistor Q4 is lower than the impurity concentration at the bottom of the channel region of driver transistors Q, , Q,.

In this way, the impurity concentration at the bottom of the channel region of access transistors Q, , Q, and driver transistors Q3, . Q
A method for making the impurity concentration lower than the lower part of the channel region of is explained as follows.

FIG. 1 shows a cross section of an access transistor forming portion. As shown in FIG. 1, a p-well 2 is formed in a semiconductor substrate 1, such as an n-type silicon (Si 2 ) substrate, and
After selectively forming a field insulating film WI3 such as a G film to isolate elements, an insulating film such as a 5iO1 film is formed by thermal oxidation on the surface of the active region surrounded by this field insulating film 3. do.

Next, an n-type impurity such as phosphorus (P) is ion-implanted into the lower part of the channel region through this insulating film with relatively high energy. Specifically, for example, P is 110ke
Ions are implanted with an energy of V. Note that, for example, arsenic (As) can be used instead of P.

This ion implantation of n-type impurities lowers the impurity concentration in the P well 2 below the chine picture region.

In FIG. 1, an X mark is placed at a position corresponding to the peak of the distribution of this implanted impurity. Here, this position is, for example, access transistor Q,,Q.

This corresponds to the region in which the depletion layer extends when a gate voltage v, > vTH and a substrate bias (2) are applied to the gate of . Specifically, the substrate bias v1 is, for example, -1,
It is 5v.

Next, after removing the above-mentioned insulating film by etching, a gate insulating film 4 such as a SiO The process is carried out according to the RAM manufacturing method to complete the desired MOS static RAM.

As described above, according to this embodiment, since the impurity concentration of the p-well 2 below the channel region of the access transistors Qs and Qa is lowered, the substrate bias effect can be suppressed by that much. Threshold voltage V of access transistors Q, , Q, due to bias effect
It is possible to suppress the increase in TH. By this, V.C.
Since CaMn can be kept low, a MOS static RAM capable of low voltage operation can be realized.

The method according to this embodiment can be applied to both a MOS static RAM using a high resistance load type memory cell and a MOS static RAM using a complete CMO3 type memory cell.

By the way, in a completely CMO3 type memo type MOS static RAM, a p
A channel thin film transistor (TPT) is used as the load. However, in the p-channel TPT using this polycrystalline Si film, the leakage current between the source and drain is large because the crystallinity of the polycrystalline Si film is not good. Therefore, various efforts have been made to reduce this leakage current. An example thereof is shown in FIG. Fifth
In the figure, reference numeral 101 is a glabellar insulating film formed on a substrate (not shown), 102 is a gate electrode of a p-channel TPT, 103 is a gate insulating film, and 104 is a polycrystalline 51w1.104a constituting a channel region.

Reference numeral 104b indicates, for example, a p-type diffusion layer constituting the source region or drain region. In this example, as shown in FIG. By providing an offset region so that the 2-type diffusion layers 104a and 104b do not overlap, leakage current between the source and drain is reduced. However, this method is not necessarily effective, so next
A method for more effectively suppressing the leakage current between the source and drain of the channel TPT will be described with reference to FIGS. 3 and 4.

In FIG. 3, reference numeral 11 is a glabella insulating film formed on a substrate (not shown), 12 is a gate electrode of a p-channel TPT, 13 is a gate insulating film, 14 is a polycrystalline Si film constituting a channel region, 14a, Reference numeral 14b indicates, for example, a p type diffusion layer constituting a source region or a drain region.

In this example, polycrystalline Si constituting the channel region is
An electrode 16 is formed on the film 14 with an insulating film 15 in between so as to face the gate electrode 12 . Then, a reverse bias is applied to this electrode 16. Here, the reverse bias applied to this electrode 16 is applied to this p-channel TPT.
This corresponds to the substrate bias for

By applying a reverse bias to the electrode process 6 in this way, the formation of an inversion layer that becomes a leak bus between the source and drain of the P-channel TPT is suppressed by the electric field effect, thereby suppressing the leakage current between the source and drain. .

That is, as shown in FIG. 4, by applying a reverse bias V (>0) to the electrode 16, the formation of an inversion layer in the polycrystal 51M14 near the interface with the insulating film 15 is prevented. This makes it possible to reduce source-drain leakage current in the subthreshold silt region.

In FIG. 4, Ec and Ev are the energies at the lower and upper ends of the conduction band, respectively, and E.

represents the Fermi energy, and 6 represents the gate voltage applied to the gate electrode 12.

According to this example, a MOS static RAM with low standby current consumption can be realized.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.

[Effects of the Invention] As explained above, the present invention has an advantage that the impurity concentration in the lower part of the channel region of the access transistor is lower than that in the lower part of the channel region of the driver transistor, so that the threshold of the access transistor due to the substrate bias effect is reduced. It is possible to suppress the increase in value voltage, thereby realizing a semiconductor memory capable of low voltage operation.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view for explaining one embodiment of the present invention, FIG. 2 is a plan view showing an example of transistor arrangement in a memory cell of a MOS static RAM, and FIG. 3 is a complete CMO3
A fourth cross-sectional view for explaining a method for reducing source-drain leakage current of a p-channel TPT used as a load of a memory cell of an O3S static RAM.
The figure is an energy band diagram for explaining the reason why the leakage current between the source and the train of the p-channel TPT is reduced, and FIG. 5 is a cross-sectional view for explaining the prior art. The main symbols in the drawings are explained as follows: semiconductor substrate, 2: P well, 3: field insulating film, 4: gate insulating film, Q, , Q,: driver transistor, Q,, Q,: access transistor.

Claims (1)

[Claims] In a semiconductor memory in which a memory cell is constituted by a flip-flop circuit including a pair of driver transistors and a pair of loads, and a pair of access transistors, the impurity concentration in the lower part of the channel region of the access transistor is A semiconductor memory characterized in that the impurity concentration is lower than that of a lower part of a channel region of a driver transistor.