JPS6053083A - 不揮発性メモリの製造方法 - Google Patents

不揮発性メモリの製造方法

Info

Publication number
JPS6053083A
JPS6053083A JP58160360A JP16036083A JPS6053083A JP S6053083 A JPS6053083 A JP S6053083A JP 58160360 A JP58160360 A JP 58160360A JP 16036083 A JP16036083 A JP 16036083A JP S6053083 A JPS6053083 A JP S6053083A
Authority
JP
Japan
Prior art keywords
layer
drain
high concentration
channel
concentration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58160360A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0478025B2 (enrdf_load_stackoverflow
Inventor
Yasuo Wada
恭雄 和田
Takaaki Hagiwara
萩原　隆旦
Akira Sato
朗 佐藤
Masao Tamura
田村　誠男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58160360A priority Critical patent/JPS6053083A/ja
Publication of JPS6053083A publication Critical patent/JPS6053083A/ja
Publication of JPH0478025B2 publication Critical patent/JPH0478025B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels

Landscapes

  • Non-Volatile Memory (AREA)
JP58160360A 1983-09-02 1983-09-02 不揮発性メモリの製造方法 Granted JPS6053083A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58160360A JPS6053083A (ja) 1983-09-02 1983-09-02 不揮発性メモリの製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58160360A JPS6053083A (ja) 1983-09-02 1983-09-02 不揮発性メモリの製造方法

Publications (2)

Publication Number Publication Date
JPS6053083A true JPS6053083A (ja) 1985-03-26
JPH0478025B2 JPH0478025B2 (enrdf_load_stackoverflow) 1992-12-10

Family

ID=15713287

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58160360A Granted JPS6053083A (ja) 1983-09-02 1983-09-02 不揮発性メモリの製造方法

Country Status (1)

Country Link
JP (1) JPS6053083A (enrdf_load_stackoverflow)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5464785A (en) * 1994-11-30 1995-11-07 United Microelectronics Corporation Method of making a flash EPROM device having a drain edge P+ implant
EP0717448A1 (en) * 1994-12-16 1996-06-19 Sun Microsystems, Inc. Asymmetric low power MOS devices
WO2000036642A1 (en) * 1998-12-18 2000-06-22 Lattice Semiconductor Corporation Method of forming a non-volatile memory device
US6215700B1 (en) 1999-01-07 2001-04-10 Vantis Corporation PMOS avalanche programmed floating gate memory cell structure
US6232631B1 (en) 1998-12-21 2001-05-15 Vantis Corporation Floating gate memory cell structure with programming mechanism outside the read path
US6282123B1 (en) 1998-12-21 2001-08-28 Lattice Semiconductor Corporation Method of fabricating, programming, and erasing a dual pocket two sided program/erase non-volatile memory cell
US6294809B1 (en) 1998-12-28 2001-09-25 Vantis Corporation Avalanche programmed floating gate memory cell structure with program element in polysilicon
US6326663B1 (en) 1999-03-26 2001-12-04 Vantis Corporation Avalanche injection EEPROM memory cell with P-type control gate
US6424000B1 (en) 1999-05-11 2002-07-23 Vantis Corporation Floating gate memory apparatus and method for selected programming thereof

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5464785A (en) * 1994-11-30 1995-11-07 United Microelectronics Corporation Method of making a flash EPROM device having a drain edge P+ implant
EP0717448A1 (en) * 1994-12-16 1996-06-19 Sun Microsystems, Inc. Asymmetric low power MOS devices
WO2000036642A1 (en) * 1998-12-18 2000-06-22 Lattice Semiconductor Corporation Method of forming a non-volatile memory device
US6214666B1 (en) 1998-12-18 2001-04-10 Vantis Corporation Method of forming a non-volatile memory device
US6232631B1 (en) 1998-12-21 2001-05-15 Vantis Corporation Floating gate memory cell structure with programming mechanism outside the read path
US6282123B1 (en) 1998-12-21 2001-08-28 Lattice Semiconductor Corporation Method of fabricating, programming, and erasing a dual pocket two sided program/erase non-volatile memory cell
US6294809B1 (en) 1998-12-28 2001-09-25 Vantis Corporation Avalanche programmed floating gate memory cell structure with program element in polysilicon
US6215700B1 (en) 1999-01-07 2001-04-10 Vantis Corporation PMOS avalanche programmed floating gate memory cell structure
US6326663B1 (en) 1999-03-26 2001-12-04 Vantis Corporation Avalanche injection EEPROM memory cell with P-type control gate
US6424000B1 (en) 1999-05-11 2002-07-23 Vantis Corporation Floating gate memory apparatus and method for selected programming thereof

Also Published As

Publication number Publication date
JPH0478025B2 (enrdf_load_stackoverflow) 1992-12-10

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