JPS6053083A - Manufacture of nonvolatile memory - Google Patents

Abstract

PURPOSE:To obtain a device having high injection efficiency and high performance by partially forming a high concentration layer by using focussed ion-beam technique. CONSTITUTION:In structure having a silicon substrate 11 and SiO212, a poly Si floating gate 13, SiO214, a poly Si control gate 15, an N<+> source 16 and a drain 17, boron ions are implanted by focussed ion beams, and a P type layer 18 in 10<17>cm<-3> surface concentration is formed. Impurity concentration in a channel region in a transistor can be brought to 1X10<16>cm<-3> or less by forming device structure so that an ion implantation layer shaped to one part of a channel and one part of a drain are superposed, and proper threshold voltage and high carrier mobility can be realized while the injection efficiency of carriers can be improved sufficiently even by applied voltage of approximately half conventional devices because of the presence of the high concentration region 18.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a novel method for manufacturing non-volatile memories of conductive conductors, and more particularly to electrically programmable extrusion-only memories (EPROMs). The present invention relates to a method of forming a highly concentrated layer in a channel region using ion beam technology to improve carrier injection efficiency and improve the performance of an EP layer.

[Background of the invention]

An example of an EPROM manufactured by the conventional technique is shown in FIG. Silicon substrate (Si
A 50-nm-thick silicon hardening film 2 formed by thermal oxidation on the ll, a 35-nm thick polycrystalline silicon film (pe7
S i ) Floating gate 3, 8Q nm thick oxide film 4 formed on the floating gate 3, 3501 m thick pe7y S i formed on the oxide film 4
Control gate 5 consisting of arsenic ions (As')
1 x 10"cm-" at 60 K e V,
A source 6 and a drain 7 consisting of an n+ diffusion layer with a junction depth of 0.4 μm and a layer resistance of 20 Ω10 formed by annealing for 20 minutes at IOOOT:', boron ions (B') at 501 eV and 5 x 10" cm- In an EPROM memory cell consisting of a channel region 8 formed by implanting two implants, the channel region 8 is implanted by applying a high voltage to the control gate 5 while applying a high electric field from the source 6 to the drain 7. The so-called hot carriers generated are attracted by the electric field of the control gate 5,
is injected into the floating gate 3, causing a threshold voltage shift. As a result, it functions as an EPROM.

The carrier injection efficiency into the floating gate 3 is
It varies greatly depending on the impurity concentration of the channel region 8. FIG. 2 shows the relationship between the impurity concentration in the channel region 8 and the efficiency of carrier injection into the floating gate 3 as a function of the voltage Vo and the drain voltage VD. It has been shown that the higher the impurity concentration, the higher the carrier injection efficiency. (Hagiwara et al., Japanese Journal of Applied Physics 16-1, p. 211 (1977); '1. I-1a
gl-1a” + Japan, J, AppZ,
P”ys, 5uppZ16-1.211 (1977)
) However, when the impurity concentration in the channel region 8 increases, (1) the carrier mobility in the channel region 8 decreases, (2) the threshold voltage V TI+ increases, (3)
This is not necessarily a good countermeasure because it has disadvantages such as an increase in drain capacity. Figure 3 shows the relationship between surface impurity concentration and field effect mobility.As the impurity concentration increases and exceeds 10'' cnr-3, the field effect mobility decreases rapidly. Therefore, the gain constant of the transistor decreases, and the switching speed increases by about three times.Also, the threshold voltage VTI (decreases depending on the surface impurity concentration). Figure 4 shows this relationship.Compared to the case where the surface impurity concentration is 10"cm-",
If X 10 "cm-" is higher than 2.5a, normal operating characteristics cannot be expected at all. Therefore, in a device with a conventional structure, for example, if the carrier injection efficiency is set to 1O-6, which is a practical level, the surface impurity concentration at which the threshold voltage is approximately IV is 2 x 10.
” cm-3, the voltage condition is Va = 3.
7V, Vo = 25V, which is an extremely high voltage, is used, which is completely disadvantageous in terms of power supply design, device design, etc.

[Summary of the invention]

The present invention was made in order to solve the problems of the prior art, and focuses on focused ion beam technology (for example, 几, L
, setiger et al. + J. Van, SCI'l'
echnol, 16 (6) 1610 (1979
) By using ), a high concentration layer is formed partially,
This realizes a high-performance device with high injection efficiency.

The present invention will be specifically described below based on Examples.

[Embodiments of the invention]

Example 1 This example provides an overview of the present invention and describes the reason why it is possible to improve the performance of a device.

FIG. 5 shows an example of the cross-sectional structure of a device according to the present invention.
nm pety Si floating gate 13, 3Q nm thick 810214, 350 nm thick I) e7
In a structure with a Si control gate 15, a + source 16, and a drain 17, boron ions (B+) are implanted with a focused ion beam to increase the surface concentration IAj 10 ”
The state in which the p-type layer 18' is formed is shown.

By adopting such a device structure, problems encountered with conventional structures (1) decrease in carrier mobility, (2) VT)
It is possible to eliminate all undesirable effects such as an increase in I and (3) an increase in drain capacity. The reason for this is that VTR
, carrier mobility gold determines the impurity concentration in the Landisk channel region k I Therefore, as is clear from the relationship shown in Figure 2, the carrier injection efficiency is 10-5-10- even with an applied voltage that is about half that of the conventional one.
'Because it can be made high enough. Shitakatsu-C
It becomes possible to realize a device having a desired VT, high carrier mobility, small drain l, and high carrier injection efficiency.

Since the focused ion beam is used, the size of the high concentration region 18 can be reduced to 0.1 μm or less, and can be significantly reduced in area compared to the area possible with conventional techniques. For example, if normal photolithography is used, the high concentration region 18
The area of the device is about 1 μm, which is the minimum processing size, so the overall device size becomes enormous. In large-scale integrated circuits (hereinafter abbreviated as VLSI) that require minute devices, the diameter of the focused ion beam tfc is, for example, 0.3 μn1.
By doing the following, it is possible to create a complete structure with structures and properties that were previously impossible.

Example 2 In FIG. 6(a), a p-type (IOO) g, 10 Ω" cm silicon substrate (hereinafter referred to as Si substrate) 11 is thermally oxidized in dry oxygen at 1000 C for 23 minutes to form an oxide film 19 with a thickness of 20 nm.
(hereinafter abbreviated as 5jOz), and further chemical vapor deposition method (C11e former cal Vapor 1)
on: A silicon nitride film (hereinafter abbreviated as Si3N4) with a thickness of 50 Ωm was deposited using the CVD method, and a 5j3N4 pattern 20-i was formed using ordinary photolithography and reactive sputter etching. Furthermore, a channel stopper layer 21 is formed by implanting B1 at a density of 5×10 12 cm −2 .

FIG. 6(b) shows that the substrate is oxidized in a wet atmosphere at 1000C to grow a field 5i0222 with a thickness of 0.8 μm, and then the 8i0z19 and 5i3N420 are removed and oxidized again in dry oxygen at 1000C. , thickness 5
Grow gate 810212 of Q 11 m, 50
After channel doping by implanting B''k of KeV, I x 10''cwr-'', LpotySi is
A floating gate 13 is shown in which the floating gate 13 is deposited to a thickness of 35 Q n In, doped with silane by thermal diffusion, and then processed into a predetermined shape by photolithography and reactive sputter etching.

In FIG. 6(C), at the end of the floating gate 13,
A state in which B+ is implanted using a focused ion beam having a thickness of 0.1 μmφ to form a high concentration layer 23 with a surface concentration of 10110l7′ is shown.

FIG. 6(d) shows that the structure is oxidized again in a 900C wet atmosphere to grow an interlayer oxide film 14 with a thickness of 8Qnm, and then a poty S film with a thickness of 350Ωm is grown by CVD.
After growing i and doping with syrin by thermal diffusion method,
The control gate 15 is formed by processing in the same manner as the floating gate 13, and the As+ is further heated to 100K.
Ion implantation was performed at a concentration of eV, lXl016cm-2, annealing was performed at 1000C for 20 minutes, and the junction depth was 0.
3μm, layer resistance 25Ω/D source 1G, drain 17
This shows the state in which it has been formed.

Figure 6(e) shows the silicone glass (hereinafter referred to as PS) produced by the CVD method.
G) 24 is formed, and after annealing, a contact hole is formed, and an aluminum wiring (hereinafter referred to as HT wiring) 25 is formed, and then hydrogen annealing is performed at 400C for 30 minutes to eliminate the interface state. shows.

By forming a non-volatile memory with this structure,
Good performance with appropriate VTR%, high carrier mobility, and high carrier injection efficiency was achieved.

Example 3 This example shows a method of forming a floating gate after forming the high concentration layer.

FIG. 7(a) shows a p-type (100) plane, 10Ω'ffi SL substrate 11, a gate 5i0212, and a field 5j.
0222, 0.0 to the structure having the channel stopper layer 21.
By using a B3 focused ion beam of 3 μmφ, surface concentration IQ
” shows a state in which a high concentration layer 23 of cm-3 is formed.

FIG. 7(b) shows the floating gate 13 and the interlayer 5i.
0214 shows the state in which the control cage 15 is formed. The structure shown in this embodiment is advantageous compared to the structure shown in the first embodiment because the additional capacitance of the control gate can be reduced.

Embodiment 4 In this embodiment, a method of forming the entire B+ high concentration seed after forming the floating gate and control gate will be described.

The eighth [] is o, i μm in a structure having a Si substrate 11, a gate (G) Sj0212, a floating gate 13, an interlayer S'0214 + a control gate) 15.
The B+ ion beam of φ is accelerated by 200 KeVK and
10" cm-2 implantation, high concentration layer 23f: The formed state is shown.

With this structure, compared to Example 3, the ion beam can be aligned and implanted with respect to the gate, so the formation position of the high concentration layer 23 can be formed with high accuracy. The advantage is that it can be done. Further, since there are few heat steps after ion implantation, diffusion of the high concentration layer 23 can be suppressed, which is advantageous in terms of device structure.

For example, pezy should be a floating gate.
A modification is also possible in which, after forming the s i layer, B+ ions are implanted from above the pety s i layer to form a high concentration layer, and then a control gate is further formed.

In FIG. 8, the reason why the junction depth of the high concentration layer 23 in the portion not covered with the goo (Glue) 13.15 is deeper than that in the lower part of the gates 13 and 15 is that during ion implantation, However, this is to partially mask the focused ions. Therefore, it is possible to improve the mother and drain breakdown voltages while maintaining the carrier injection efficiency.

Example 5 In this example, a highly concentrated layer is formed on the side wall of a floating gate using a focused ion beam, and
A method for lateral diffusion by heat treatment will be described.

In a structure having a floating gate 139 interlayer 5i0214 + control gate 15, a high concentration layer 23 is formed at the end of the control gate 15 using a B+ convergent ion beam of 0.2 μιφ, and
After annealing and diffusion for 30 minutes, source 16. A state in which a drain 17 is formed is shown. According to this embodiment,
The feature is that high-performance devices can be realized even if the alignment accuracy of the focused ion beam is somewhat low.

Example 6 This example shows the impurity concentration range of the high concentration layer. The solid line a shown in Fig. 10 shows the relationship between the impurity concentration of the highly concentrated layer and the junction breakdown voltage, and is
In this case, the voltage is about 60V, but at 10"cm-3 it is about 15V.
At V-1018cm-'', the voltage decreases to about 5v.

On the other hand, the injection voltage is the practical carrier injection efficiency 'el
When O=, as already shown by the broken line in Fig. 1θ, approximately 2X
1017 exceeds the junction breakdown voltage. Therefore, the impurity concentration of the high concentration layer 23 is 2×1017 cm−3 or less.

Further, since a practical write voltage is about 30 V or less, the minimum impurity concentration was 5×10”on=.

〔Effect of the invention〕

As shown in the above embodiments, according to the present invention, while maintaining the characteristics of VTR precision settings and high carrier mobility,
Since high carrier injection efficiency can be achieved, electrically programmable non-volatile read-only memories (EP, OAJ, etc.) with good fx and characteristics can be realized.

[Brief explanation of drawings]

FIGS. 1 to 4 are explanatory diagrams of the prior art, and FIGS. 5 to 1 are diagrams showing embodiments of the present invention. 1.11...Silicon substrate, 2,4,12.14°1
9.22...Silicon oxide film, 3, 5, 13°15-
...Gate conductor, 6, 7. 16, 17.n'' diffusion layer, 8... Channel doped layer 18.23... High concentration layer by focused ion source, 20... Silicon nitride film, 24... Phosphorus glass, 25... Aluminum Wiring, 21...Channel stopper. II2] Z Figure 71 K 4 *'t:=2'lJ X jL (to
``tqn-'') Fig. 3 Surface J bladder pressure (lo''6c-') 'ff141Z1 Surface bladder pressure (tO'' snoring S Fig. 6 (C) Fig. 6 (C) ) (d) (e) Fig. 7 (α) (b) Fig. δ Fig. 9 Fig. 10 Fig. 7 Name 19119 with the person who corrects the manufacturing method of non-volatile memory 11f'l Patent applicant name Name '51
01 (:l, Rei H: +1
Subject of person's correction The detailed description of the invention in the specification, the brief description of the drawings, and the contents of the drawing supplement = key = inside = old amendment. , the ion implantation layer formed in at least a part of the channel overlaps with a part of the drain, so it is corrected to J. (2) Ibid., page 13, line 3, 1-cm-3. ”
Insert the following between ``Effects of the Invention'' and the fourth line 〇Example 7 In this example, the high concentration layer was properly placed within the channel, and the high concentration layer at least overlapped with the drain. If necessary, it may be extended to the source side. Figure 11 (
In this explanatory diagram, a) shows a plan view of an information storage device in a nonvolatile memory, and in a structure having a source 16, a drain 17, and a channel 26,
It is shown that a highly concentrated layer 23 formed by a focused ion beam is formed at the drain end of the channel. FIG. 11(b) shows a structure including a source 16, a drain 17, and a channel 26ff, including a highly concentrated layer 23 formed by a focused ion beam. In this example, the high concentration layer 23 is shown to be in contact with the tray/end and extend to the source side. As shown in this example, the highly concentrated layer formed by the focused ion beam needs to be in contact with at least a portion of the drain. That is, [2 does not necessarily need to be located at the center of the drain end of the channel 26, and may partially cover the field oxide film 22 for device insulation. In addition, when ion implantation is performed with a focused ion beam at the edge of the gate, as shown in Example 2, if the ion implantation is performed after forming a gate, a large secondary electron current is generated when the gate end is irradiated with the focused ion beam. Since it can be observed, it can also be used as a monitor when forming a highly concentrated layer 23 at the end of the channel 26 on the drain side using a focused ion beam. (3) Ibid., page 13, line 13, “Figure 10” was replaced with “Figure 11.”
Corrected to ``Figure''. (4) Add attached sheet Figure 11 (al) and Figure 11 (b).

Claims (1)

[Claims] A feature is that a p-high concentration impurity diffusion layer is formed by ion implantation using a focused ion beam in at least a part of the channel region under the 70-ting gate of an electrically writable nonvolatile memory. A method for manufacturing non-volatile memory.