JP4365568B2 - Doping method and semiconductor device using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a doping method for forming a pn junction in a manufacturing process of a semiconductor device and a semiconductor device using the same, and more particularly, a high concentration doping method having an extremely shallow junction, and a MOS type using the same. The present invention relates to a field effect transistor (Metal-Oxide-Semiconductor Field Effect Transistor: hereinafter referred to as a MOSFET).
[0002]
[Prior art]
Until now, semiconductor LSI (Large Scale Integration) devices have achieved high integration and high speed simultaneously by miniaturization of processing dimensions. Even in the case of MOSFETs, technical improvements have been made to reduce the size of the element, but as the channel length becomes shorter, a phenomenon unfavorable in terms of element performance, called the short channel effect and the hot carrier phenomenon, becomes prominent.
[0003]
In order to suppress the phenomenon that adversely affects the performance of these elements, it is necessary to reduce the depth of the source and drain junctions. Further, in order to increase the current drive capability of the transistor, the resistance value (layer resistance) of the source and drain doping layers needs to be as low as possible. Therefore, in a fine MOSFET, this requirement is satisfied by increasing the carrier concentration of the doping layer. That is, in a fine MOSFET, the shallow junction and low resistance of the source and drain must be achieved at the same time.
[0004]
Conventionally, a combination of low energy ion implantation and rapid thermal annealing (A. Ono et al .: 2000 Symposium on VLSI Technology Digest of Technical Papers, 14), plasma doping (Bunzo Mizuno: Applied Physics, Vol. 70, No. 12, p1458-1462, 2001), Elevated source / drain by selective epitaxial growth (Katsuhiko Muto: November issue of electronic materials) Separate volume / 2002 VLSI manufacturing / test equipment guidebook, p. 95-104, 2001), solid layer diffusion (Eiichi Murakami et al .: JP-A-8-167658), laser doping (K. Shibahara et al. : 2001 Solid State Devices and Materials, p.236).
[0005]
[Problems to be solved by the invention]
However, the junction depth obtained by the above conventional technique is 20 nm at most and the layer resistance is about 400Ω / □. In the future, in order to achieve miniaturization of transistors, there is a need for a technique for forming an extremely shallow and high-concentration doping layer that exceeds the limitations of these conventional techniques.
[0006]
In addition, these processes, particularly short-time steep heat treatment, require a large amount of electric power to perform and are not only problematic from the viewpoint of energy efficiency, but also include high dielectric constant gate insulating film materials and metal gate materials. This is also the cause of the inability to use new materials with limited heat resistance.
[0007]
Furthermore, since all of the above conventional techniques introduce impurity atoms into the semiconductor through a stochastic process such as ion implantation or thermal diffusion, it is unavoidable that statistical variations in the position and concentration of impurity atoms are inevitably avoided. . Due to this, the variation in the characteristics of the fabricated elements has emerged as a serious problem along with the miniaturization of the elements. However, there is no known doping method that can solve this, and a new method is required.
[0008]
The present invention has been proposed in view of the above, and can realize shallow junction and low resistance of the source and drain, can improve the energy efficiency in manufacturing, and can also be used as a material with limited heat resistance. It is another object of the present invention to provide a doping method that can be applied and does not vary the characteristics of the device, and a semiconductor device using the doping method.
[0009]
[Means for Solving the Problems]
To achieve the above object, an invention according to claim 1, the charge transfer to the cluster over whether we silicon surface deposited on a silicon surface, a carrier is generated in the vicinity of the silicon surface, the cluster, TaSi ₁₂ , ReSi ₁₆ , a silicon cluster containing a group 5 atom of the periodic table, and a silicon cluster containing a group 3 atom of the periodic table .
[0010]
Further, the invention according to claim 5, the charge transfer to the deposited cluster over whether we silicon surface on the silicon surface, produced by generating carriers in the vicinity of the silicon Table surfaces, the cluster, TaSi _12, A semiconductor element characterized by being one of ReSi ₁₆ , a silicon cluster containing a group 5 atom of the periodic table, and a silicon cluster containing a group 3 atom of the periodic table .
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0012]
FIG. 1 is a diagram for explaining the principle of the present invention. The present invention attaches molecules or clusters acting as a carrier supply source to a semiconductor surface, and forms a very thin high-concentration carrier conductive layer near the inside of the semiconductor surface by charge transfer from the molecule or cluster as the carrier supply source to the semiconductor surface. Form.
[0013]
In the formation of the high-concentration carrier conductive layer, the type of carrier is determined by the difference in chemical potential between the molecule or cluster serving as the carrier supply source and the semiconductor surface. As shown in FIG. 1A, the energy level of the highest occupied molecular orbital (HOMO) of a molecule or cluster attached to the semiconductor surface, which is a carrier supply source, is higher than the lower end of the conduction band of the semiconductor surface. For example, a charge transfer in which a negative charge is induced from the molecule or cluster to the semiconductor surface occurs, a positive charge is generated in the molecule or cluster, and electrons are attracted near the surface of the semiconductor to form a carrier conductive layer. . In this case, the carrier of the carrier conduction layer is conduction electrons.
[0014]
In the opposite case, that is, as shown in FIG. 1B, the energy level of the lowest unoccupied molecular orbital (LUMO) of a molecule or cluster attached to the semiconductor surface is higher than that of the valence band on the semiconductor surface. If it is low, a charge transfer that induces a negative charge from the semiconductor surface to the molecule or cluster occurs, a negative charge is generated in the molecule or cluster, holes are attracted near the surface of the semiconductor, and the carrier conduction layer is Form. In this case, the carrier of the carrier conductive layer is a hole. In the former case, if the substrate is a p-type semiconductor, a pn junction is formed between the molecules or clusters. In the latter case, if the substrate is an n-type semiconductor, the pn junction is formed between the molecules or clusters. Will be formed.
[0015]
At this time, as a molecule or cluster serving as a carrier supply source, a molecule or a molecular orbital of the molecule or cluster satisfying the above energy condition with respect to a semiconductor valence band or conduction band can be used. In particular, when the semiconductor is silicon (Si), Si clusters containing transition metal atoms, Si clusters containing Group 5 atoms of the periodic table such as arsenic and antimony, or periodic rules such as boron and gallium. A Si cluster containing a group 3 atom can be used.
[0016]
Among these, for example, a silicon cluster TaSi ₁₂ composed of 12 Si atoms including one tantalum atom has a high electron accepting property, a large ability to be negatively charged, and acts as an acceptor. In contrast, the silicon cluster ReSi ₁₆ containing rhenium atoms has a large electron supply capability and acts as a donor. Similarly, a silicon cluster containing a group 5 atom of the periodic table such as arsenic or antimony functions as a donor, and a silicon cluster containing a group 3 atom of the periodic table such as boron or gallium functions as an acceptor.
[0017]
Since the thickness of this carrier source (molecules or clusters attached to the semiconductor surface) is at the same level as the size of the molecules or clusters, in sub-nanometers, this pn junction is the same as the thickness of the inversion layer, It is an extremely shallow depth of nanometers.
[0018]
In addition, in the present invention, doping can be realized only by attaching molecules or clusters to the semiconductor surface, and activation treatment at high temperature is not required. Therefore, heat resistance such as a high dielectric constant gate insulating film material or a metal gate material is improved. New materials with restrictions can be used without problems. In addition, power consumption necessary for device manufacture can be reduced.
[0019]
In the junction formed by the conventional ordinary doping method, the carrier supply source exists inside the carrier conductive layer, so that the mobility is lowered and the resistance is increased due to defects caused by doping and scattering by dopant atoms. . On the other hand, in the present invention, since the carrier supply source and the carrier conductive layer are separated, the scattering by the dopant atoms is essentially small. Also, if the kinetic energy when depositing molecules or clusters on the ideal semiconductor surface without defects is lowered and soft landing is performed, the semiconductor surface will not be physically damaged and the semiconductor surface without defects will be maintained. Can do. Accordingly, there is no reduction in mobility, and the layer resistance is a value expected for an ideal semiconductor surface. That is, according to the present invention, a junction having extremely low layer resistance can be formed.
[0020]
In addition, in the conventional method, impurity atoms are randomly introduced into the semiconductor, whereas in the method of the present invention, molecules and clusters serving as a carrier supply source are attached to the semiconductor surface with high density. Clusters are densely arranged on the surface, and as a result, extremely small doping with statistical fluctuation can be achieved.
[0021]
At this time, it is not necessary for the molecules and clusters to be the carrier supply source to be directly attached to the semiconductor surface, and even if they are attached via an appropriate insulator thin film, the above principle is established as it is and the same effect can be obtained. . Rather, by interposing the insulating film, the surface level of the semiconductor surface can be eliminated, and the efficiency of charge transfer can be increased. When the semiconductor is Si, for example, a thermal oxide film can be used as the insulating film.
[0022]
Next, as an experiment to prove the principle of carrier generation by charge transfer according to the present invention, a cluster for generating carriers is deposited on a silicon substrate on which four electrodes are formed by a microfabrication technique. Measurements were made. As a cluster for generating carriers, TaSi ₁₂ which is one of metal-encapsulating silicon clusters is used in the first embodiment (see Japanese Patent Laid-Open No. 2000-327319). This silicon cluster TaSi ₁₂ is synthesized using an ion trap device (see Japanese Patent No. 2869517), and the synthesized silicon cluster TaSi ₁₂ is a vacuum in which a silicon substrate for four-terminal electrical measurement is stored from the ion trap device. It was transported to the apparatus by an ion guide or the like, and deposited on an n-type silicon substrate having a resistivity of 10 Ω · cm with a low energy of 2 eV and a dose of 2.5 × 10 ¹⁴ cm ⁻² . The silicon surface on which the silicon cluster TaSi ₁₂ was deposited was observed with an STM (scanning tunneling microscope). Hall measurement was also performed for mobility measurement. All measurements were performed at room temperature in an ultra-high vacuum (1 × 10 ⁻⁷ Pa).
[0023]
As a result of observation by STM, silicon cluster TaSi ₁₂ was deposited almost on the surface of the silicon substrate of the sample, and the coverage was about 90%. As a result of the 4-terminal measurement, the layer resistance was about 300Ω / □. Further, since the Hall coefficient is positive, the current bearer was a hole, and the mobility of the hole was 100 cm ² / V · s. Therefore, it was found that the charge transfer from the silicon cluster TaSi ₁₂ to the silicon substrate occurs with an efficiency of almost 100%. From the above, the principle of the present invention was proved.
[0024]
Next, in the second embodiment, silicon hydride cluster ions AsSi ₅ H containing arsenic atoms are formed on the surface of a p-type silicon substrate (resistivity: 10 Ω · cm) on which four electrodes are formed by the microfabrication technique. _x ⁺ was deposited at a dose of 2.5 × 10 ¹⁴ cm ⁻² . The number of hydrogen atoms x was 2 to 6, and the coverage was about 60%. At this time, according to the four-terminal measurement, the layer resistance of the conductive layer induced on the sample surface was about 200Ω / □, and the electron mobility was 200 cm ² / V · s.
[0025]
Next, a third embodiment of the present invention will be described with reference to FIGS. In this third embodiment, a MOS transistor 11 as schematically shown in FIG. 2 was produced in the process of FIG. First, an oxide film having a thickness of 5 nm was formed on the surface of the Si substrate 3 by thermal oxidation in dry oxygen to obtain a gate insulating film 4. On top of this, polycrystalline Si was deposited and processed into a gate electrode 1 having a length of 1 micron by photolithography. Boron ions with an energy of 50 keV are implanted into Si substrate 3 by a normal ion implantation method at 1 × 10 ¹⁵ / cm ² , and after an activation treatment at 900 ° C. in a normal heat treatment furnace, source 2a and drain 2b Formed. The distance between the gate electrode 1 and the source 2 a and drain 2 b is 1 micron. 1 × 10 ¹⁴ / cm ^{2 of} silicon clusters TaSi ₁₂ was deposited on the entire surface (gate electrode 1 and gate insulating film 4) of this structure to form source / drain extension regions. Thereafter, a silicon nitride film 9 was deposited as a protective film for stabilization, and a silicon cluster TaSi ₁₂ was embedded. Thereafter, a window was opened in the silicon nitride film 9 again by optical lithography, an aluminum electrode 10 was deposited, and a MOS transistor 11 was completed.
[0026]
FIG. 4 is an enlarged view of the vicinity of the source and drain of the MOS transistor 11 in FIG. 2 and shows the state of charge transfer from the silicon cluster TaSi ₁₂ (silicon cluster 7 used for carrier generation) to the surface of the silicon substrate 3. In the MOS transistor 11 shown in FIG. 4, the silicon cluster TaSi ₁₂ receives electrons in contact with the source 2a and the drain 2b and easily charges the negative charge 6, while the source 2a and the drain 2b have a positive charge 8 Is charged. That is, carriers are generated in the vicinity of the semiconductor surface by charge transfer from the clusters attached to the semiconductor surface to the semiconductor surface. Thus, since the thickness of the carrier supply source (silicon cluster 7 attached to the semiconductor surface) is the same level as the size of the cluster, it is possible to form a junction in which the layer resistance of the silicon cluster 7 is extremely low. The MOS transistor 11 showed good characteristics.
[0027]
In the above example, the molecules or clusters are made to volume on the semiconductor surface via the insulator thin film. However, the insulator film may be deposited after the molecules or clusters are directly attached to the semiconductor surface. .
[0028]
【The invention's effect】
According to the present invention, it is possible to sufficiently achieve a junction depth of 10 nm and a layer resistance of 830 Ω / □ required for a source / drain junction of a MOSFET having a gate length of 18 nm, which is expected to be mass-produced in 2010. In addition, the present invention has a remarkable effect on shallow junction and low resistance.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining the principle of the present invention.
FIG. 2 schematically shows a structure of a MOSFET manufactured in a third embodiment of the present invention.
FIG. 3 is a diagram showing a manufacturing process of a MOSFET manufactured in a third embodiment of the present invention.
4 is an enlarged view of the vicinity of the source and drain of the MOS transistor of FIG. 2;
[Explanation of symbols]
1 Gate electrode 2a Source 2b Drain 3 Semiconductor substrate (silicon substrate)
4 Gate insulating film 5 Channel 6 Negative charge induced in cluster by charge transfer 7 Silicon cluster used for carrier generation 8 Positive charge induced in substrate by charge transfer

Claims (6)

The charge transfer to the deposited cluster over whether we silicon surface on the silicon surface, a carrier is generated in the vicinity of the silicon surface,
The cluster is any one of TaSi ₁₂ , ReSi ₁₆ , a silicon cluster containing a group 5 atom of the periodic table, and a silicon cluster containing a group 3 atom of the periodic table.
A doping method characterized by the above. On the silicon surface provided with an insulating film, depositing a cluster through the insulator film, the doping method according to claim 1. Depositing an insulator film after depositing the cluster to the silicon surface, the doping method according to claim 1. 2. The doping method according to claim 1, wherein the group 5 atom of the periodic table is arsenic or antimony, and the group 3 atom of the periodic table is boron or gallium. Produced by generating carriers near the silicon surface by charge transfer from the cluster attached to the silicon surface to the silicon surface,
The cluster is any one of TaSi ₁₂ , ReSi ₁₆ , a silicon cluster containing a group 5 atom of the periodic table, and a silicon cluster containing a group 3 atom of the periodic table.
The semiconductor element characterized by the above-mentioned. The semiconductor element according to claim 5, wherein the group 5 atom of the periodic table is arsenic or antimony, and the group 3 atom of the periodic table is boron or gallium .

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