JPS6049443A - ラッチ回路 - Google Patents

ラッチ回路

Info

Publication number
JPS6049443A
JPS6049443A JP59078826A JP7882684A JPS6049443A JP S6049443 A JPS6049443 A JP S6049443A JP 59078826 A JP59078826 A JP 59078826A JP 7882684 A JP7882684 A JP 7882684A JP S6049443 A JPS6049443 A JP S6049443A
Authority
JP
Japan
Prior art keywords
transistor
circuit
node
coupled
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59078826A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0325817B2 (enExample
Inventor
ドナルド・バーンズ・キレイ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS6049443A publication Critical patent/JPS6049443A/ja
Publication of JPH0325817B2 publication Critical patent/JPH0325817B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318552Clock circuits details
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037Bistable circuits
    • H03K3/0375Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • H03K3/356017Bistable circuits using additional transistors in the input circuit
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • H03K3/356017Bistable circuits using additional transistors in the input circuit
    • H03K3/356052Bistable circuits using additional transistors in the input circuit using pass gates
    • H03K3/35606Bistable circuits using additional transistors in the input circuit using pass gates with synchronous operation

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Shift Register Type Memory (AREA)
  • Logic Circuits (AREA)
JP59078826A 1983-08-01 1984-04-20 ラッチ回路 Granted JPS6049443A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US51933883A 1983-08-01 1983-08-01
US519338 1983-08-01

Publications (2)

Publication Number Publication Date
JPS6049443A true JPS6049443A (ja) 1985-03-18
JPH0325817B2 JPH0325817B2 (enExample) 1991-04-09

Family

ID=24067873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59078826A Granted JPS6049443A (ja) 1983-08-01 1984-04-20 ラッチ回路

Country Status (3)

Country Link
EP (1) EP0137165B1 (enExample)
JP (1) JPS6049443A (enExample)
DE (1) DE3471855D1 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9417591D0 (en) * 1994-09-01 1994-10-19 Inmos Ltd Scan testable double edge triggered scan cell

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4004170A (en) * 1975-04-29 1977-01-18 International Business Machines Corporation MOSFET latching driver
US3993919A (en) * 1975-06-27 1976-11-23 Ibm Corporation Programmable latch and other circuits for logic arrays

Also Published As

Publication number Publication date
EP0137165A1 (en) 1985-04-17
DE3471855D1 (en) 1988-07-07
JPH0325817B2 (enExample) 1991-04-09
EP0137165B1 (en) 1988-06-01

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